PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 545

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
3.4.2 HBE and Latency
3.4.3 Interrupts
3.4.4 Timestamp Events
If the software fails to provide a new buffer of data in time, and both DMA buffers
empty out, the SPDO hardware raises the UNDERRUN flag in SPDO_STATUS.
Transmission switches over to the use of the next buffer, but the data transmitted is
from the previously transmitted buffer. IF UDR_INTEN is asserted, an interrupt will be
generated. The UNDERRUN flag is sticky - it will remain asserted until the software
clears it by writing a ‘1’ to ACK_UDR.
A lower level error can also occur when the limited size internal buffer empties out
before it can be refilled across the data bus. This situation can arise only if insufficient
bandwidth is allocated to SPDO from the bus arbiter. In this case, the Highway
Bandwidth Error (HBE) error flag is raised.
If the arbiter is set up with an insufficient latency guarantee, a situation can arise that
requested data will not arrive in time, (when a new output sample is due). In that case
the HBE error is raised, and the last sample for each channel will be repeated until
the new buffer is refreshed. The HBE condition is sticky, and can only be cleared by
an explicit ACK_HBE. This condition indicates an incorrect setting of the arbiter.
The arbiter needs to guarantee that the maximum latency required by the SPDO
block can always be met.
Given an output data rate f
interval. The arbiter should be set to have a latency so that the buffer is refilled before
a sample interval expires. Refer to
Table 3: SPDO Block Latency Requirements
The SPDO block generates an interrupt if one of the following status bit flags, and its
corresponding INTEN flag are set: BUF1_EMPTY, BUF2_EMPTY, HBE,
UNDERRUN. See Offset
All these status flags are ‘sticky’, i.e. they are asserted by hardware when a certain
condition occurs, and remain set until the interrupt handler explicitly clears them by
writing a ‘1’ to the corresponding ACK bit in SPDO_CTL. The SPDO hardware takes
the flag away in the clock cycle after the ACK is received. This allows immediate
return from interrupt once performing an ACK.
SPDO exports event signals associated with audio transmission to the central
timestamp/timer function on-chip. The central timestamp/timer function can be used
to count the number of occurrences of each event or timestamp the occurrence of the
event or both. The event will be a positive edge pulse with the duration of the event to
be greater than or equal to 200 ns. The specific event exported is as follows:
f
32.000
44.100
48.000
96.000
s
(kHz)
Rev. 2 — 1 December 2004
0x10 9000 SPDO_STATUS
s
in samples/sec, 2 x 32 bits are required each sample
1/f
31250
22675
20833
10416
s
(nSec)
Table 3
for example latency requirements.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
for details.
Chapter 17: SPDIF Output
Max. latency (9/
281
204
187
94
PNX15xx Series
f
s)
(uSec)
17-7