PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 517

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 9: Audio Output Port Registers
12NC 9397 750 14321
Product data sheet
Bit
21:8
7
6
5
4
3
2
1
0
Offset 0x11 0008
31
30
29
28:19
18:17
Symbol
Unused
UDR_INTEN
HBE_INTEN
BUF2_INTEN
BUF1_INTEN
ACK_UDR
ACK_HBE
ACK2
ACK1
SER_MASTER
DATAMODE
CLOCK_EDGE
Unused
NR_CHAN
AO_SERIAL—DTL Clock Domain
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
…Continued
-
0
0
0
0
0
0
0
0
0
0
0
-
00
Value
Rev. 2 — 1 December 2004
Description
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read
UNDERRUN Interrupt Enable.
0 = No interrupt for UNDERRUN condition
1 = Interrupt if an UNDERRUN error occurs.
HBE Interrupt Enable:
0 = No interrupt for HBE condition
1 = Interrupt if a data bus bandwidth error occurs.
Buffer 2 Empty Interrupt Enable:
0 = No interrupt when DMA buffer is empty.
1 = Interrupt if DMA buffer 2 in memory is empty.
Buffer 1 Empty Interrupt Enable:
0 = No interrupt when DMA buffer 1 is empty.
1 = Interrupt if DMA buffer 1 in memory is empty.
Write a 1 to clear the UNDERRUN flag and remove any pending
UNDERRUN interrupt request. ACK_UDR always reads 0.
Write a 1 to clear the HBE flag and remove any pending HBE
interrupt request. ACK_HBE always reads as 0.
Write a 1 to clear the BUF2_EMPTYflag and remove any pending
BUF2_EMPTY interrupt request. AO_BASE2 is then used to fetch
buffer1 data from memory. ACK2 always reads 0.
Write a 1 to clear the BUF1_EMPTY flag and remove any pending
BUF1_EMPTY interrupt request. AO_BASE1 is then used to fetch
buffer1 data from memory. ACK1 always reads 0.
0 = The D/A subsystem is the timing master over the Audio Out
serial interface. SCK and WS act as inputs.
1 = AO is the timing master over serial interface. SCK and WS act
as outputs. This mode is required for 4, 6 or 8 channel operation.
The SER_MASTER bit should only be changed while Audio Out is
disabled i.e.,TRANS_ENABLE = 0.
0 = Data is transmitted MSB first.
1 = Data is transmitted LSB first.
0 = The parallel-to-serial converter samples WS on positive edges
of SCK and outputs data on the negative edge of SCK.
1 = The parallel-to-serial converter samples WS on negative edges
of SCK and outputs data on positive edges of SCK.
To ensure software backward compatibility unused or reserved bits must
be written as zeros and ignored upon read
00 = Only SD[0] is active.
01 = SD[0] and SD[1] are active.
10 = SD[0], SD[1], and SD[2] are active.
11 = SD[0], SD[1], SD[2] and SD[3] are active.
Each SD output receives either 1 or 2 channels depending on
TRANS_MODE. Non-active channels receive 0 value samples. In
mono modes, each channel of a SD output receives identical left
and right samples.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Chapter 15: Audio Output
.
15-17