F84045 Asiliant Technologies, F84045 Datasheet - Page 88

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.7.1. CPU SMM Differences
The major difference between the Intel and Cyrix SMM support is the handling of the SMIACT# / SMIADS# pin. For
the Intel CPU it goes low before the first SMM bus cycle and stays low until after the end of the final bus cycle. It can
be used as a static mode indicator. It will not transition during bus cycles and has plenty of setup time (many clock
cycles). For the Cyrix CPU SMIADS# is generated instead of ADS#, and is on a bus cycle by bus cycle basis.
For Intel SMM A20M# must be taken high to access upper memory. This is done across the link in the CS4041 when
SMIACT# goes low. It is returned to its original state when SMIACT# goes back high. KEN# is also sampled in SMM
mode for the Intel CPUs. A Config bit (Index 94h bit 3) determines whether SMM space is cached. FLUSH# is also
optionally generated upon SMM entry, but this is normally not required.
For the Cyrix CPU, A20M# is ignored in SMM mode, and assumed high. The CS4041 does not modify A20M# for
Cyrix SMM. KEN# and FLUSH# are left unaffected also.
5.7.2. CPU Clock Differences
The major differences between the CPU clock support involves changing and stopping the clock. On some CPUs the
clock cannot be changed at all, except under tight control (which is possible with some synthesizers). With other
CPUs, a STPCLK# function allows the CPU clock to be changed or stopped. On still others the clock is static and may
be changed at any time. The power control logic has options for clock control. See section 5.14 for details.
5.7.3. CPU L1 Cache Options
The cache protocol is basically the same for all CPUs. The L1 Write Back cache functions are a superset of the Write
Through functions. There are some options to support subtle CPU differences:
5.7.4. CPU Pin Connections
CLOCK. The 4041 provides a separate clock pin, CPUCLK, for the CPU which should have minimal skew relative to
other clocks such as SCLK into the 4041 (i.e., use same buffer chip for clock buffering). CPUCLK is the same as
SCLK except that CPUCLK can be stopped without affecting the other clock signals in the system. Also, some CPUs
require that the clock not be running before VCC reaches a valid level. This must be accomplished externally by gating
CLKIN with PWRGOOD, or by using PWRGOOD to disable the buffer that provides CPUCLK.
Revision 1.0
WB / WT# pin
WriteProtect
Write Protect function
2/10/95
Multifunction pin allowing certain areas to be forced write t hrough.
Multifunction pin allowing a line to be write protected in the CPU cache.
Options on how write protecting the BIOS is handled. It may be either non-cache in
the CPU cache, or EADS# generated on CPU write cycles. If the WB WT# pin is
used, write protected areas are always write through.
Subject to change without notice
87
Preliminary
Functional Description
CS4041