F84045 Asiliant Technologies, F84045 Datasheet - Page 50

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
3A-3B
3C
3D
3E
Revision 1.0
1:0
3:2
5:4
7:6
1:0
3:2
5:4
7:6
This register supplies the data for pins which are selected as general purpose Output bits.
0
1
2
3
4
5
7:6
Bits
(Reserved)
Multifunction Pin Selection Register A.
This register determines the function of 4 pins. In the future, more functions may be added. When
added to input pins, these bits should be programmed as "General Purpose Inputs", which disables
their other functions.
LDEV1# pin usage. T his pin is always an input.
LDEV2# pin usage. This pin is always an input.
GPA pin usage. This pin is always an input.
GPB pin usage. This pin is always an output.
Multifunction Pin Selection Register B.
This register determines the function of 4 pins, all of which are outputs.
RAS6# pin usage. This pin is always an output.
RAS7# pin usage. This pin is always an output.
GPC pin usage. This pin is always an output.
GPD pin usage. This pin is always an output.
General Purpose Output data register.
Data for RAS6# pin when programmed as a general purpose output bit.
Data for RAS7# pin when programmed as a general purpose output bit.
Data for GPB pin when programmed as a general purpose outpu t bit.
Data for GPC pin when programmed as a general purpose output bit.
Data for GPD pin when programmed as a general purpose output bit.
Data for FLUSH# pin when programmed as a general purpose output bit.
Function of the FLUSH# pin.
2/10/95
00
01
00
01
00
01
00
01
00
01
00
01
00
01
00
01
00
01
10
11
Description
Gen Pur Input
#LDEV1
Gen Pur Input
LDEV2#
Gen Pur Input
14 MHz clock
WB / WT# pin
ISAEN
RAS6#
MA12
RAS7#
IOC4045# (4045 chip sel)
WPROT# (CPU wrt prot)
CACHECS#
DRAMCS#
ISAEN
FLUSH#
General Purpose Output bit.
IOCS0# (I/O Chip Select 0)
General Purpose Output Bit
Subject to change without notice
49
Default = 00
Default = 00
Default = 00
10
11
10
11
10
11
10
11
10
11
10
11
10
11
10
11
14MHz clock (to pwr mgmt & BUSCLK)
(Reserved)
KB Inhibit input
External Event 1 (to pwr mgmt)
XDIO#
External Event 0
IRQ12 (Mouse Interrupt)
General Purpose Output
MEMCS0# (memory chip select 0)
General Purpose Output
MEMCS1# (memory chip select 1)
General Purpose Output
IOCS0# (I/O chip select 0)
General Purpose Output
IOCS1# (I/O chip select 1)
General Purpose Output
Configuration Registers
Preliminary
CS4041