F84045 Asiliant Technologies, F84045 Datasheet - Page 125

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.13.5. Chip Selects and I/Os, & Misc
GPIO. I/O. General Purpose I/O bits. These may be an input or an output, controlled individually.
IOCS0#. I/O chip select 0. Output of the Programmable I/O decode 0. May be a chip select or a strobe, and active
for reads and/or writes. See the Programmable I/O decode section for details.
IOCS1#. I/O chip select 1.
MEMCS0#. Memory chip select 0. Active when Programmable Memory decode 0 is active. It is a chip select only,
and is active for both read and write cycles. It will be valid regardless of the destination bus of the cycle.
MEMCS1#. Memory chip select 1. See above.
IRQ12. Mouse interrupt. Normally sent across the link, it may be an output pin directly.
KBINHIBIT. 8042 keyboard controller inhibit (keylock). When low, the 8042 will not accept keyboard input.
IOCSIPC#. I/O Chip select for the SIPC. This is a straight decode of A10:15. The pin is low when all are low. Used
as the upper address decode for the 4045 SIPC.
ISAEN. AT bus enable. Active when an ISA bus cycle is active, or when DGNT# is low (indicating that the a DMA
or ISA master is in progress). This pin is high if either ATEN is active or DGNT# is active. This pin is active high
since the power up state of the multifunction pin is high, and the buffers must be enabled at power up to read the ROM.
XDIO#. XD bus I/O. When this pin is low, I/O cycles will be directed to the XD bus instead of the SD bus. It has no
effect for memory cycles or VL cycles. It is intended for future use for on-board devices residing on the XD bus.
5.13.6. Pin Selection
The two "GP select" registers select the function of 8 of the multifunction pins. Each is a 2 bit field. An additional 2
bits in the "GPout data" select the function of the FLUSH# pin. The STPCLK# function is selected in the power
management section. The MCLK and MDATA functions are selected by the mouse enable bit, and the HITM#
function is controlled in the CPU register.
The "GPout data" supplies the output bits when a multifunction pin is programmed as a general purpose output. Bits 7
& 6 select the FLUSH function.
Revision 1.0
Table 5.32: Multifunction Pin Programming Registers
GPout data
GPin data
GP select
GP select
Function
Table 5.31: Multifunction Pin Function Programming
Pin Number
STPCLK#
LDEV1#
LDEV2$
FLUSH#
MDATA
RAS6#
RAS7#
MCLK
2/10/95
GPA
GPB
GPC
GPD
(Reserved)
flushsel1
gpDsel1
gpBsel1
D7
Out only
Out only
Out only
Out only
Out only
Out only
Out only STPCLK# (O) CLKSPEED (O)
OC or in
OC or in MDATA (OC)
In only
In only
In only
flushsel0
gpDsel0
gpBsel0
D6
Function 1 (00) Function 2 (01) Function 3 (10) Function 4 (11)
Subject to change without notice
FLUSH# (O)
MCLK (OC)
DRAMCS#
WB / WT#
WPROT#
RAS6#
RAS7#
GPin
GPin
GPin
FLUSH#
GPAsel1
MDATA
gpCsel1
D5
gpAsel0
gpCsel0
MCLK
124
GPD
CACHECS#
D4
(Reserved)
14MHz (I)
IOCSIPC#
LDEV1#
LDEV2#
ISAEN
ISAEN
GPin
GPin
-
ldev1sel1
ras6sel1
GPC
D3
-
KBINHIBIT
MEMCS0#
MEMCS1#
IOCS0#
IOCS1#
IOCS0#
14MHz
XDIO#
IRQ12
ldev1sel0
ras7sel0
GPA
GPB
D2
ldev0sel1
LDEV1#
ras6sel1
RAS7#
D1
(Reserved)
Preliminary
Functional Description
GPout
GPout
GPout
GPout
GPout
GPout
EXT1
EXT0
ldev0sel0
LDEV0#
ras6sel0
RAS6#
D0
CS4041