F84045 Asiliant Technologies, F84045 Datasheet - Page 20

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

MASTER#
CPU & Local Bus control signals
SMIACT# / SMIADS#
ADS#
W / R#
D / C#
M / IO#
RDY#
BRDY#
KEN#
FLUSH#
BLAST#
EADS#
HITM#
WBACK#
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IN
IN
I/O
I/O
I/O
I/O
I/O
I/O
OUT
OUT
I/O
I/O
IN
OUT
ISA bus master signal. Indicates that an ISA master has the bus. The 4041 uses this
Indicates SMM memory accesses. The function depends on the CPU type. For Intel
Address Strobe. Input for CPU and local master cycles, output for DMA and ISA
Write/Read status signal. Input for CPU and local master cycles, output for DMA
Data/Code status signal. Input for CPU and local master cycles, output for DMA
Memory/IO status signal. Input for CPU and local master cycles, output for DMA
Non Burst ready. O utput when 4041 is a slave. Input from a local bus slave or
Burst Ready. Output when 4041 is a slave. Input from a local bus slave or external
Cache Enable to the CPU. Always driven. Only local DRAM is cached in the CPU.
Flush L1 cache. May be used when entering SMM.
Burst Last. Driven (low) for DMA and ISA master cycles.
External Address Strobe. Used to snoop and invalidate the 486 cache on DMA and
Hit Modified. Input from the CPU indicating that the result of the snoop is a dirty
Writeback. Output to the 4045 and VL bus slots based on the HITM# inpu t,
to determine the difference between DMA and ISA master cycles. It is used in
determining the timing for IOCHRDY generation.
SMM it is an SMIACT# status signal. For Cyrix SMM it is the ADS# for SMM
cycles.
master cycles.
and ISA master cycles.
and ISA master cycles.
and ISA master cycles.
external cache controller.
cache controller.
Certain areas may be marked non-cacheable.
ISA master memory cycles.
Optionally driven active for writes to write protected memory.
cache line, i.e., the CPU cache contains the only valid copy of data that an
alternate master is attempting to read. See also WBACK# below.
indicating that the CPU needs to perform an L1 cache writeback operation
before an alternate master receives the data that the master is attempting to read.
The 4041 determines when to allow the writeback to occur in relation to other
system activity. The bus cycle from an alternate master will be aborted to allow
the CPU to write back the data. When the 4041 has control of the local bus (ISA
masters or DMA) it will back off the bus while WBACK# is low. As required
by VL bus protocol, a local bus master (LBM) must be capable of aborting a
cycle (without RDY# or BRDY#), then restarting the cycle again after the
writeback operation is completed. In response to WBACK#, the 4045 drops
HOLD long enough to give control the CPU, then re-asserts HOLD and gives
control back to the alternate master after the CPU has finished the writeback
operation and re-asserted HLDA.
Subject to change without notice
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Floated when a local master has the bus.
Preliminary
Pin Descriptions
CS4041