F84045 Asiliant Technologies, F84045 Datasheet - Page 67

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
Revision 1.0
0A
index
0A
3:0
6:4
7
function
dma clk
Bits
DMA Clock selection.
MHz SCLK.
Clock select for DMA controllers. Also determines 4045 internal BUSCLK for p erformance control
2/10/95
(Index 08h) and IPC I/O wait states (Index 01h). The IPC may optionally further divide this clock
by 2 before sending it to the DMA controllers (it should be programmed to do so via Index 01 bit
0).
clock should be about 8MHz, which the IPC megacell will then divide by 2 (if so programmed
via Index 01 bit 0) to get the 4 MHz used by the DMA controllers. Higher clock rates may be
used at the risk of incompatibilities with the DMA devices. External BUSCLK for the ISA bus
comes from the 4041 (Index 07h). 4045 internal BUSCLK doesn't need to be in phase with 4041
external BUSCLK, although the two BUSCLKs normally will be programmed to be the same
frequency.
(Reserved)
External RTC
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
int RTC
The source of the clock is SCLK, which is the 1X CPU clock, or 14.3 MHz. The resulting
D7
Description
SCLK/10
SCLK/8
SCLK/6
(Reserved)
(Reserved)
(Reserved)
14.31818 MHz divided by 1.5 (9.545 MHz)
14.31818 MHz divided by 2 (7.159 MHz)
CLKIN/5
CLKIN/4
CLKIN/3
CLKIN/2.5
CLKIN/2
CLKIN/1.5
(Reserved)
1111
0
1
D6
-
Subject to change without notice
Default = 00. Typical setting = 09h for 33.3 MHz SCLK, or 0Ah for 25
D5
-
(80 MHz SCLK)
(66.67 MHz)
(50 MHz SCLK)
(40MHz SCLK)
(33MHz SCLK)
(25MHz SCLK)
(20MHz SCLK)
(16MHz SCLK)
DMA clock is 14.31818MHz divided by 3.5 (4.091 MHz)
Internal RTC enable
External RTC. 32KX1 becomes the IRQ8# input.
66
D4
-
dma clk3
D3
dma clk2
D2
dma clk1
Configuration Registers
Preliminary
D1
dma clk0
D0
CS4041