F84045 Asiliant Technologies, F84045 Datasheet - Page 75

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Subject to change without notice
System Level Functions
4.13. CPU Capabilities for Power Management
4.13.1 CPU Clock Control
Some CPUs allow the CPU clock to be stopped completely, while others may require a minimum clock frequency as
well as a maximum. Of the CPUs that allow the clock to be stopped, some allow it to be stopped instantly, while others
require a handshake protocol to be followed. System power savings can often be achieved simply by slowing or
stopping the CPU clock and the corresponding chipset clocking, even with CPUs that do not support a System
Management Mode.
For further information, refer to Sections 1.1, 4.1 and 5.7.
4.13.2 System Management Mode (SMM)
Most newer 486-class CPUs support one of several possible types of System Management Mode (SMM), based on a
system Management Interrupt (SMI) that puts the CPU into SMM. SMM, in turn, is recognized by the CS4041
chipset, which can make special DRAM areas available exclusively for use while running in SMM. SMM, in
conjunction with power management software, allows system power consumption to be reduced without having to turn
the system completely off or reboot the system every time full system operation is needed. CS4041 supports a variety
of event detectors and timers for generating SMI#, both to signal the power management software to suspend
appropriate parts of the system, and to wake up from a suspended state.
CS4041 also supports the I/O restart capability usually found in CPUs that have SMM. I/O restart means that when the
CPU starts an I/O operation in an address range that has been previously programmed for I/O restart, the 4041 issues
SMI instead of performing an I/O cycle on the ISA bus. The CPU then goes into SMM and provides information
sufficient to allow the SMM routine to determine which I/O resource was being addressed. The SMM routine can then
perform any peripheral power-up and initialization needed. On exit from SMM, the CPU will re-execute the I/O
operation. I/O restart is useful in systems where peripherals can be selectively powered down transparently to the end
user for power savings during system operation.
For further information, refer especially to Section 5.14. See also Sections 1.1, 5.3.1, 5.6, 5.7, 5.13, and 6.11.1. 0V
Suspend (also known as suspend to disk) is discussed in Section 6.3.1.
Revision 1.0
2/10/95
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Preliminary
CS4041