F84045 Asiliant Technologies, F84045 Datasheet - Page 10

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Table 2.1
Table 2.2
Table 3.1
Table 3.2
Table 4.1
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 5.8
Table 5.8.1
Table 5.9
Table 5.10
Table 5.11
Table 5.12
Table 5.13
Table 5.14
Table 5.15
Table 5.16
Table 5.17
Table 5.18
Table 5.19
Table 5.20
Table 5.21
Table 5.22
Table 5.23
Table 5.24
Table 5.25
Table 5.26
Table 5.27
Table 5.28:
Table 5.29:
Table 5.30:
Table 5.30.1
Table 5.31
Table 5.32
Table 5.33
Table 5.34
Table 5.34.1
Table 5.35
Table 5.36
Table 5.37
Table 5.38
Table 5.39
Revision 1.0
84041 Pin List................................ ................................ ................................ ................................ .......... 15
84045 Pin List................................ ................................ ................................ ................................ .......... 17
84041 and 84045 I/O Port Summary ................................ ................................ ................................ .......29
84041 and 84045 Configuration Register Summary ................................ ................................ ................ 30
CPU Chip Reset Signal Routing ................................ ................................ ................................ .............. 69
Clock Divider ................................ ................................ ................................ ................................ .......... 75
GATEA20 & KBRESET Source. ................................ ................................ ................................ ............ 76
Bus Owner Indication ................................ ................................ ................................ .............................. 78
I/O Decode Lower Bit Mask (A6:0) ................................ ................................ ................................ ........ 79
I/O Decode Upper Bit Mask (A15:7) ................................ ................................ ................................ .......79
DRAM Shadow Bit Encoding ................................ ................................ ................................ ................. 81
Programmable Memory Decode Size and Placement ................................ ................................ .............. 82
User/SMM Space Shadow RAM Bits ................................ ................................ ................................ ......84
CPU Address Bit Usage ................................ ................................ ................................ ........................... 90
Cache Pin Usage ................................ ................................ ................................ ................................ ......91
Tag Bit Mapping ................................ ................................ ................................ ................................ ......92
Data SRAM Configurations ................................ ................................ ................................ ..................... 94
TAG SRAM Configurations ................................ ................................ ................................ .................... 94
Suggested Cache Timing Modes and RAM Speeds ................................ ................................ ................ 94
Cache Modes. ................................ ................................ ................................ ................................ ........ 102
Cache Test Window Location ................................ ................................ ................................ ................ 104
512K Cache Test Mode Mapping When In The Lower Meg ................................ ................................ .104
RAS and CAS usage ................................ ................................ ................................ .............................. 107
DRAM Block Starting Address ................................ ................................ ................................ ............. 107
DRAM Size Options ................................ ................................ ................................ .............................. 108
CPU Address Assignments For Interleaving and Non-Interleaving ................................ ....................... 110
Address Multiplexing ................................ ................................ ................................ ............................ 110
Staggered Refresh Set Assignment ................................ ................................ ................................ ........ 113
Suggested DRAM Timing Modes ................................ ................................ ................................ ......... 114
Default signal states ................................ ................................ ................................ ............................... 118
Programmable Timing Parameters ................................ ................................ ................................ ......... 118
Determine Which Drive Is Active ................................ ................................ ................................ .......... 119
Fast IDE Register Set ................................ ................................ ................................ ............................. 121
Drive Speed Selection ................................ ................................ ................................ ............................ 121
Register Settings for IDE Timing ................................ ................................ ................................ .......... 121
Programming for Standard IDE Modes ................................ ................................ ................................ .122
Typical Timing Parameters ................................ ................................ ................................ .................... 122
Multifunction Pin Function Programming ................................ ................................ ............................. 124
Multifunction Pin Programming Registers ................................ ................................ ............................ 124
SMM Status and Enable Registers ................................ ................................ ................................ ......... 129
Activity Timer Selectable Functions ................................ ................................ ................................ ......129
Time Base Selection ................................ ................................ ................................ .............................. 130
CPU Slow Clock Programming ................................ ................................ ................................ ............. 130
SMM Timer Resolutions and Max Time-Outs ................................ ................................ ...................... 130
Event Functions ................................ ................................ ................................ ................................ .....131
External Pin Event Modes In Index Register 8Fh ................................ ................................ .................. 132
Event Fixed I/O Address Ranges ................................ ................................ ................................ ........... 132
2/10/95
Subject to change without notice
List of Tables
11
Preliminary
List of Tables
CS4041