F84045 Asiliant Technologies, F84045 Datasheet - Page 63

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Addr
71
80-8F
80
81
82
83
84-86
87
88
89
8A
8B
8C-8E
8F
92
A0-A1
C0-DF
F0-F1
Revision 1.0
0
1
2
3
7:4
Port
92
Bits
Real Time Clock Data Port.
Reading or writing this port will read or write the RTC register pointed to by the last write to port 70.
DMA Page Registers
These ports are contained in the IPC megacell. They provide A16-23 for 8-bit DMA accesses and
A17-23 for 16-bit DMA.
Read/Write, but not used during normal system operation. This port is written by BIOS routines to
Channel 2 page register
Channel 3 page register
Channel 1 page register
Not used.
Channel 0 page register
Not used.
Channel 6 page register
Channel 7 page register
Channel 5 page register
Not used.
Refresh page register. Bits 1-3 from this register define the state of SA17-19 during refresh. Since
Fast CPU reset & GATEA20.
Fast CPU reset. A 0 to 1 transition activates a CPU reset.
Fast GATEA20. ORed with other GATEA20 signals (from 8042, for instance).
(Reserved).
RTC Password Protect. If Index 0Ch bit 1 is 0, writing to this bit has no effect and the bit always
(Reserved). read as 0s.
Interrupt Controller #2 (IRQ8-15).
These ports are contained in the IPC megacell. The interrupt controller does NOT respond to ports
A2-BF.
DMA Controller #2 (16 bit DMA).
These ports are cont ained in the IPC megacell. Only the even numbered ports are used. Reads or
writes to the odd numbered ports will access the same register as its corresponding even numbered
port.
387 Error Reset.
Writing to either F0 or F1 causes the error latch (which also generates IRQ13) to be cleared. The data
is ignored.
2/10/95
indicate BIOS status. A pair of HEX 7 segment LEDs are often put on test boards to display this
information.
refresh is hidden, the 4045 has no access to SA16 and LA20-23 during refresh. Bit 0 and bits 4-7
are not used. All bits are read/write. Typical setting = 00h.
reads as 0. If Index 0Ch bit 1 is 1, writing 1 to this bit has the following effects: (a) All further
reads and writes to the RTC CMOS RAM locations 38:3F are disabled, and (b) this bit remains 1
(reads back as 1) and cannot be cleared except by a system reset (PWRGOOD cycling, causing
SYSRESET to cycle).
0
1
D7
-
Description
Drive A20M- low to the CPU (if all other A20M- sources are low).
Force A20M- high to the CPU, causing the CPU to leave A20 unmasked.
D6
-
Subject to change without notice
D5
-
RTC passpro
62
D4
D3
-
D2
-
Fast gatea20
D1
Preliminary
I/O Port Addresses
fast reset
D0
CS4041