F84045 Asiliant Technologies, F84045 Datasheet - Page 61

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

3.4. 84045 I/O Port Addresses
Note: "Default" register values refer to the power-on hardware defaults established automatically following hardware
reset, before any alternate values have been written by the BIOS. "Typical" values refer to typical settings for normal
system operation.
Addr
00-0F
20-21
22
23
26
27
40-43
60
Revision 1.0
Bits
DMA controller #1 (8 bit DMA).
These ports are contained in the IPC megacell. The DMA controller will NOT respond to accesses to
10-1F (in the original AT 00-0F repeats at 10-1F).
Interrupt Controller #1 (IRQ0-7).
These ports are contained in the IPC megacell. The Interrupt controller does NOT respond to ports
22-3F.
Configuration register Address Port.
Write only port which holds the address of the Chips and Technologies Index register to be accessed
through I/O port 23. This register must be written before each access to port 23, even if the same
index register is being accessed twice in a row.
Configuration register data.
Accessing this port accesses the Configur ation register pointed to by port 22. A second access to port
23 without writing port 22 in between will be ignored. Unless otherwise noted in the register
descriptions, reserved or undefined index registers should not be written to, and reserved bits within a
defined index register should be written as zero (or written with the same value previously read).
SMM Configuration Register Address Port
Write only. The address written here is stored separately from port 22. This register is used as the
config register index when port 27 is read or written.
SMM Configuration Register Data Port
Accessing this port accesses the Configuration register pointed to by port 26. A second access to port
27 without writing to port 27 in between will be ignored. The "accessed" bit is separate for the port
26/27 and 22/23 windows.
Timer Chip (8254).
These ports are contained in the IPC megacell. The timer does NOT respond to ports 44-4F.
Keyboard and Mouse Interrupt Clear.
Reading from port 60h resets the keyboard and mouse interrupt latches, IRQ1 and IRQ12. All other
data read/write functions for this port are implemented in the 4041.
2/10/95
Description
Subject to change without notice
60
Preliminary
I/O Port Addresses
CS4041