F84045 Asiliant Technologies, F84045 Datasheet - Page 73

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

The timing modes provided allow for timing optimization based on DRAM speed and CPU speed. A separate, less
aggressive timing mode may be selected for VL masters since they are a less controlled (by the system designer)
variable in the timing equation, and may not be as fast as the particular CPU used by the system designer. The timing
modes are:
256K, 1M, 4M, and 16M deep DRAMs are supported. Direct drive is provided for two banks. Beyond that, buffering
is dependent on the capacitive load provided by the DRAM configuration. 12/10 addressing is supported for 4Mx4
DRAM. 13/11 addressing is supported for 16M deep DRAMs by using a multifunction pin for MA12.
The DRAMs may be placed on the local data bus directly or buffered with 4 F245s. A buffer control signal is provided
on a multifunction pin.
Throughout this document, the term “local DRAM” means DRAM controlled directly by the RAS-CAS signals of the
4041, not memory slaves residing on the VL bus and utilizing an LDEV# signal to claim memory cycles.
For further information, see Section 5.10.
4.9. Cache Controller
The cache controller has the following features:
The cache controller allows for cost performance tradeoffs. Full speed modes are supported for performance, and
slower modes are supported for cost effective systems, especially with single bank caches and higher CPU speeds.
Single bank 2-1-1-1 is supported.
A system board is easily upgradeable from a single bank to a dual bank cache without any jumpers on the data SRAMs.
Some upgrade configurations may require a jumper on the tag RAMs since it connects directly to the CPU address bus
and must match the cache size.
The BIOS may autoconfigure the cache, determining the size and configuration of the data RAMs and making sure the
tag RAM size matches, as well as determining its width (which determines the cacheability range).
For further information, see Sections 5.5.2, 5.9, and 5.13.
Revision 1.0
Burst Reads: 3-2-2-2, 4-3-3-3, or 5-4-4-4 timing modes
Single writes: 1 or 2 wait state.
Burst Writes: 3-2-2-2, or 4-3-3-3.
RAS to CAS timing: 2 or 3 T states (1.5 or 2.5 for 3-2-2-2 burst reads).
RAS pulse width for refresh cycles: 3 or 4 T states.
RAS precharge: 2 or 3 clocks
Direct Mapped.
Standard SRAMs
External Tag RAM
Internal tag comparator
Operation up to 50MHz
16 byte line size
64K, 128K, 256K, 512K, and 1M cache size
Write back or write through
Single bank or dual bank (word interleaved) cache.
2-1-1-1, 2-2-2-2, or 3-2-2-2 reads. (2-2-2-2 mode for single bank only)
0ws or 1ws writes
2-1-1-1 or 3-2-2-2 burst writes.
2/10/95
Subject to change without notice
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System Level Functions
Preliminary
CS4041