F84045 Asiliant Technologies, F84045 Datasheet - Page 102

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Note: The 1WS option for clean-to-dirty tag write is not currently implemented. It is included for general illustration
Revision 1.0
only. The clean-to-dirty tag write is always 2WS.
2/10/95
Single Bank 2-1-1-1 burst write
Dual Bank 2-1-1-1 burst write
Single Bank 3-2-2-2 burst write
Dual Bank 3-2-2-2
4-2-2-2 burst write (Single Bank Shown)
L2 Cache
Write Hit
Clean line, WB (change from clean to dirty)
DIRTY
TAGWE#
TAGOE#
Dirty line, WB
CA2
CA3A
CWEA#
CA3A
CA3B
CWEA#
CWEB#
CA2
CA3A
CWEA#
CA3A
CA3B
CWEA#
CWEB#
CA2
CWEA#
A4:31
TAG
CWEn#
BRDY#
A4:31
TAG
DIRTY
CRDn#
CWEn#
BRDY#
A4:31
T1
T1
T2
1 Wait State tag write
tag
Figure 5.10: L1 Cache Write Back
T1
(CPU, etc)
Master
Figure 5.9: L2 Cache Write Hit
L1 Cache Write Back (CPU burst write)
0 wait state write
Subject to change without notice
tag
D0:31
A4:16
(128K cache)
A4:16
(128K cache)
T1
T1
a read hit, single word
A2:31
101
tag
2 Wait State tag write
tag
tag
CWEA#
CWEB#
CA3A
CA3B
CA2
T1
1 wait state write
data RAM
Bank A
data RAM
Bank B (when
Present)
T1
Preliminary
Functional Description
T1
CS4041