F84045 Asiliant Technologies, F84045 Datasheet - Page 115

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.10.7. Programming the Timing Modes.
The following table gives the suggested programming for 60 and 70nS DRAMs at 33, 40 and 50MHz. The DRAM
specs used were a composite of the more commonly available DRAMs. Many DRAMs are faster on many parameters
than the composite. A few are slower. The 60nS DRAMs assume 15nS tCAC and the 70nS DRAMs assume 20nS
tCAC. Other DRAM speeds, such as 50 and 80 are supported. In many cases the 50nS parts are not much better than
60nS parts for page mode cycles. 80nS parts may require some parameters to be relaxed slightly.
The table is reasonably conservative. Some of the parameters may be set more aggressively (some are noted with an
"*"). Often EXTREMELY aggressive timing parameters work very well. If extremely aggressive timing is used, it is
suggested that a more conservative mode be in register 1E, which is used by VL masters (it is also used for DMA and
ISA masters). Since there will be a wide variety of VL-Masters some are likely to be close to the edge of the spec (or
violate it completely). CPUs are often much faster than spec and are shipped with the system, which may allow a more
aggressive timing mode. The ability of the user to install an upgrade CPU, which may not have better-than-worst-case
timing should be kept in mind.
The RAS to CAS delay would be set to a 1 for 80nS DRAMs at 50MHz, and also at 33MHz with 3-2-2-2 mode.
Revision 1.0
Parameter
Burst Reads
Burst Writes
Single Writes
RAS to CAS
RAS Precharge
RAS
Refresh
Table 5.23: Suggested DRAM Timing Modes
2/10/95
Total register
RAS to CAS
Burst Writes
Single Write
RAS low on
Burst Reads
RAS Prech
Parameter
ref
Low
* Conservative setting. Next faster setting is slightly aggressive.
10 bit(s) 60
on
Index
1:0
all
6
4
2
5
7
1.5/2 clocks
Subject to change without notice
3 (1WS)
2 clocks
non-cache
3-2-2-2
3-2-2-2
00
0
0
0
0
0
0
0
3
70
1*
01
33MHz
0
0
0
0
0
60
1*
01
0
0
0
0
0
cache
2.5/3 clocks
70
1*
01
0
0
0
0
0
114
4 (2WS)
3 clocks
4-3-3-3
4-3-3-3
1
4
non-cache
60
1*
41
1
0
0
0
0
70
1*
61
40MHz
1
0
0
1
0
60
41
1
1
0
0
0
0
cache
5-4-4-4
70
61
1
1
0
0
1
0
2
-
-
-
-
-
non-cache
60
71 F1
2
1
1
0
1
0
70
50MHz
2
1
1
0
1
1
(Reserved)
60
71
2
1
1
0
1
0
Preliminary
cache
Functional Description
3
-
-
-
-
-
F1
70
2
1
1
0
1
1
CS4041