F84045 Asiliant Technologies, F84045 Datasheet - Page 56

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
87
88
89
Revision 1.0
index
index
87
88
89
2:0
7:3
2:0
3
4
6:5
7
7:0
timerA cntrl WakeAFast
INTA base
function
function
timerA
Bits
Interrupt Acknowledge 1 base.
automatically whenever the INTC2 interrupt vector base is changed by software. This register is used
by the 4041 to determine whether an INTA cycle was caused by IRQ8:15 or not, since the 4041 does
not receive the IRQ pins directly but does have access to the interrupt vector returned to the CPU
during an INTA cycle. (See also Indexes 80h and 82h.) If the INTA vector matches the contents of
this register (bits 7:3), it came from IRQ8:15. If not, the interrupt came from IRQ0:7. The vector
itself (bits 2:0) then indicates which specific IRQ within the group is being acknowledged. Writing
the interrupt vector base via A0h and A1h automatically causes the value in this index register to
match the new value, but writing to this index does not alter the value written via A0h and A1h since
the actual INTC2 resides in the 4045. Software or BIOS normally should never write to this register
(Index 87h), since its value automatically tracks whatever is written to INTC2.
(Reserved)
Specifies the upper 5 bits of the interrupt acknowledge vector which corresponds to IRQ8:15.
TimerA Control Register
This register provides the rate and function of TimerA and the function of the WakeA Event. TimerA
may also cause an SMI. This is enabled in the SMI enable register.
TimerA count rate.
(Reserved)
Slow Down the clock on TimerA timeout.
(Reserved)
Switch to the full speed CPU clock on WakeA Events.
TimerA Count Register
Writing to this register sets the count value. A value between 1 and FF may be written. This value is
reloaded in the timer each time an EventA occurs. Reading this register gives the current value of the
timer.
programmed here.
TimerA restart value.
2/10/95
Typically set (via ports A0h and A1h) to 01110 by DOS, or 01011 by Windows.
intabase7
With the rate set to OFF, the current value of the timer will be the restart value last
000
001
010
011
100
101
110
111
0
1
0
1
tmrA7
D7
D7
Description
Off. Counter remains at restart value.
64uS
1mS
16mS
256mS
4 seconds
64 seconds
(Reserved)
Disabled
TimerA timing out will cause the CPU clock to be slowed down. This is done by
Disabled.
WakeA event switches the clock back to full speed.
intabase6
tmrA6
either the internal divider or external synthesizer, as specified elsewhere.
D6
D6
Subject to change without notice
intabase5
tmrA5
D5
D5
TimerASlow
Typical setting = 70h for use with DOS, subject to change
intabase4
55
tmrA4
D4
D4
intabase3
tmrA3
D3
D3
rateA2
tmrA2
D2
D2
-
rateA1
tmrA1
Configuration Registers
Preliminary
D1
D1
-
rateA0
tmrA0
D0
D0
-
CS4041