MC9S08GT16CFB Freescale Semiconductor, MC9S08GT16CFB Datasheet - Page 75

• Manufacturer Part Number: MC9S08GT16CFB
• Manufacturer: Freescale Semiconductor

Specifications of MC9S08GT16CFB

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 1KB
• # I/os (max): 36
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

LVDRE — Low-Voltage Detect Reset Enable
LVDSE — Low-Voltage Detect Stop Enable
LVDE — Low-Voltage Detect Enable
5.8.8
This register is used to report the status of the low voltage warning function, and to configure the stop mode
behavior of the MCU.
LVWF — Low-Voltage Warning Flag
LVWACK — Low-Voltage Warning Acknowledge
Freescale Semiconductor
This read/write bit enables LVDF events to generate a hardware reset (provided LVDE = 1).
Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates
when the MCU is in stop mode.
This read/write bit enables low-voltage detect logic and qualifies the operation of other bits in this
register.
1
The LVWF bit indicates the low-voltage warning status.
The LVWACK bit indicates the low-voltage warning acknowledge.
Writing a 1 to LVWACK clears LVWF to 0 if a low voltage warning is not present.
V
LVWF will be set in the case when V
1 = Force an MCU reset when LVDF = 1.
0 = LVDF does not generate hardware resets.
1 = Low-voltage detect enabled during stop mode.
0 = Low-voltage detect disabled during stop mode.
1 = LVD logic enabled.
0 = LVD logic disabled.
1 = Low voltage warning is present or was present.
0 = Low voltage warning not present.
LVW
.
System Power Management Status and Control 2 Register (SPMSC2)
Figure 5-9. System Power Management Status and Control 2 Register (SPMSC2)
Power-on reset:
Any other reset:
LVD reset:
Read:
Write:
LVWF
Bit 7
0
0
0
(1)
(1)
1
Supply
= Unimplemented or Reserved
LVWACK
MC9S08GB/GT Data Sheet, Rev. 2.3
6
0
0
0
0
transitions below the trip point or after reset and V
LVDV
0
U
U
5
Reset, Interrupt, and System Control Registers and Control Bits
LVWV
0
U
U
4
PPDF
3
0
0
0
U = Unaffected by reset
PPDACK
0
2
0
0
0
Supply
PDC
1
0
0
0
is already below
PPDC
Bit 0
0
0
0
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