MC9S08GT16CFB Freescale Semiconductor, MC9S08GT16CFB Datasheet - Page 64

MC9S08GT16CFB

Manufacturer Part Number
MC9S08GT16CFB
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC9S08GT16CFB

Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SCI/SPI
Program Memory Type
Flash
Program Memory Size
16KB
Total Internal Ram Size
1KB
# I/os (max)
36
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.08V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

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Chapter 5 Resets, Interrupts, and System Configuration
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of
the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address just recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR.
Typically, the flag should be cleared at the beginning of the ISR so that if another interrupt is generated by
this same source, it will be registered so it can be serviced after completion of the current ISR.
5.5.2
External interrupts are managed by the IRQSC status and control register. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.
5.5.2.1
The IRQ pin enable (IRQPE) control bit in the IRQSC register must be 1 for the IRQ pin to act as the
interrupt request (IRQ) input. When the pin is configured as an IRQ input, the user can choose the polarity
of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD),
and whether an event causes an interrupt or only sets the IRQF flag (which can be polled by software).
When the IRQ pin is configured to detect rising edges, an optional pulldown resistor is available rather than
a pullup resistor. BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is
configured to act as the IRQ input.
64
External Interrupt Request (IRQ) Pin
Pin Configuration Options
STACKING
ORDER
UNSTACKING
5
4
3
2
1
ORDER
1
2
3
4
5
* High byte (H) of index register is not automatically stacked.
7
Figure 5-1. Interrupt Stack Frame
INDEX REGISTER (LOW BYTE X)
MC9S08GB/GT Data Sheet, Rev. 2.3
CONDITION CODE REGISTER
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
ACCUMULATOR
*
TOWARD HIGHER ADDRESSES
TOWARD LOWER ADDRESSES
0
SP AFTER
INTERRUPT STACKING
SP BEFORE
THE INTERRUPT
Freescale Semiconductor

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