MC9S08GT16CFB Freescale Semiconductor, MC9S08GT16CFB Datasheet - Page 137

• Manufacturer Part Number: MC9S08GT16CFB
• Manufacturer: Freescale Semiconductor

Specifications of MC9S08GT16CFB

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 1KB
• # I/os (max): 36
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
ASL opr8a
ASLA
ASLX
ASL oprx8,X
ASL ,X
ASL oprx8,SP
ASR opr8a
ASRA
ASRX
ASR oprx8,X
ASR ,X
ASR oprx8,SP
BCC rel
BCLR n,opr8a
BCS rel
BEQ rel
BGE rel
BGND
BGT rel
BHCC rel
BHCS rel
BHI rel
BHS rel
BIH rel
BIL rel
BIT #opr8i
BIT opr8a
BIT opr16a
BIT oprx16,X
BIT oprx8,X
BIT ,X
BIT oprx16,SP
BIT oprx8,SP
BLE rel
BLO rel
BLS rel
BLT rel
BMC rel
Source
Form
Arithmetic Shift Left
(Same as LSL)
Arithmetic Shift Right
Branch if Carry Bit Clear
Clear Bit n in Memory
Branch if Carry Bit Set
(Same as BLO)
Branch if Equal
Branch if Greater Than or
Equal To
(Signed Operands)
Enter Active Background
if ENBDM = 1
Branch if Greater Than
(Signed Operands)
Branch if Half Carry Bit
Clear
Branch if Half Carry Bit
Set
Branch if Higher
Branch if Higher or Same
(Same as BCC)
Branch if IRQ Pin High
Branch if IRQ Pin Low
Bit Test
Branch if Less Than
or Equal To
(Signed Operands)
Branch if Lower
(Same as BCS)
Branch if Lower or Same
Branch if Less Than
(Signed Operands)
Branch if Interrupt Mask
Clear
Operation
Table 8-1. HCS08 Instruction Set Summary (Sheet 2 of 7)
MC9S08GB/GT Data Sheet, Rev. 2.3
Commands Until GO, TRACE1, or
Waits For and Processes BDM
(CCR Updated but Operands
C
Branch if (Z) | (N ⊕ V) = 0
Branch if (Z) | (N ⊕ V) = 1
Branch if (C) | (Z) = 1
Branch if (C) | (Z) = 0
Branch if (N ⊕ V ) = 1
Branch if IRQ pin = 1
Branch if IRQ pin = 0
Branch if (N ⊕ V) = 0
Branch if (C) = 1
b7
b7
Branch if (C) = 0
Branch if (C) = 1
Branch if (Z) = 1
Branch if (H) = 0
Branch if (H) = 1
Branch if (C) = 0
Branch if (I) = 0
Description
Not Changed)
(A) & (M)
Mn ← 0
TAGGO
b0
b0
0
C
V H I N Z C
– – – – – – REL
– – – – – –
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – INH
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
0 – –
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
– –
– –
on CCR
Effect
–
HCS08 Instruction Set Summary
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
9ED5
9EE5
9E68
9E67
1D
C5
D5
2C rr
1B
2E rr
A5
B5
E5
38
48
58
68
78
37
47
57
67
77
24 rr
11
13
15
17
19
1F
25 rr
27 rr
90 rr
82
92 rr
28 rr
29 rr
22 rr
24 rr
2F rr
F5
93 rr
25 rr
23 rr
91 rr
dd
ff
ff
dd
ff
ff
dd
dd
dd
dd
dd
dd
dd
dd
ii
dd
hh ll
ee ff
ff
ee ff
ff
5+
5
1
1
5
4
6
5
1
1
5
4
6
3
5
5
5
5
5
5
5
5
3
3
3
3
3
3
3
3
3
3
2
3
4
4
3
3
5
4
3
3
3
3
3
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