MC9S08GT16CFB Freescale Semiconductor, MC9S08GT16CFB Datasheet - Page 61

• Manufacturer Part Number: MC9S08GT16CFB
• Manufacturer: Freescale Semiconductor

Specifications of MC9S08GT16CFB

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 1KB
• # I/os (max): 36
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 5 Resets, Interrupts, and System Configuration
5.1
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts
in the MC9S08GB/GT. Some interrupt sources from peripheral modules are discussed in greater detail
within other sections of this data manual. This section gathers basic information about all reset and
interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral
systems with their own sections but are part of the system control logic.
5.2
Reset and interrupt features include:
5.3
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector ($FFFE:$FFFF). On-chip peripheral modules are disabled and I/O pins are initially configured
as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the condition code
register (CCR) is set to block maskable interrupts so the user program has a chance to initialize the stack
pointer (SP) and system control settings. SP is forced to $00FF at reset.
The MC9S08GB/GT has seven sources for reset:
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Multiple sources of reset for flexible system configuration and reliable operation:
— Power-on detection (POR)
— Low voltage detection (LVD) with enable
— External RESET pin with enable
— COP watchdog with enable and two timeout choices
— Illegal opcode
— Serial command from a background debug host
Reset status register (SRS) to indicate source of most recent reset
Separate interrupt vectors for each module (reduces polling overhead) (see
Power-on reset (POR)
Low-voltage detect (LVD)
Computer operating properly (COP) timer
Illegal opcode detect
Background debug forced reset
The reset pin (RESET)
Clock generator loss of lock and loss of clock reset
Introduction
Features
MCU Reset
MC9S08GB/GT Data Sheet, Rev. 2.3
Table
5-1)
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