S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet - Page 93

• Manufacturer Part Number: S5935QF
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5935QF

• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5935 – PCI Product
Table 38. Valid External Boot Memory Contents
LOADING FROM SERIAL NV MEMORIES
SNV tied high indicates that a serial nv memory (or no
external device) is present. When serial nv memories
are used, data transfer is performed through a two-
wire, bidirectional data transfer protocol as defined by
commercial serial EEPROM/Flash offerings. These
devices have the advantages of low pin counts, small
package size, and economical price.
A serial nv memory is considered valid if the first serial
accesses contain the correct per-byte acknowledg-
m e n t s ( s e e F i g u r e 3 ) . I f t h e s e r i a l p e r - b y t e
acknowledgment is not observed, the S5935 deter-
mines that no external serial nv memory is present
and the AMCC default Configuration Register values
are used.
Two pins are used to transfer data between the S5935
PCI controller and the external serial memory: a serial
clock pin, SCL, and a serial data pin, SDA. The serial
clock pin is an output from the S5935, and the serial
data pin is bidirectional. The serial clock is derived by
dividing the PCI bus clock by 512. This means that the
frequency of the serial clock is approximately 65 kHz
for a 33-MHz PCI bus clock.
Note: When a serial boot device is used, EA9 is de-
fined as a SCL divide by control pin.
If EA9 = 1 then SCL = PCLK/512
If EA9 = 0 then SCL = PCLK/8
This pin should be pulled high.
Communications with the serial memory involve sev-
eral clock transitions. A start event signals the
beginning of a transaction and is immediately followed
AMCC Confidential and Proprietary
0040h-41h
Address
0050h
0052h
0053h
0051
C2h, C1h or C0h
not FFFFh
Data
FFh
E8h
10h
This is the location that the S5933 PCI Controller will load a customized vendor ID. (FFFFh
is an illegal vendor ID.)
This is the least significant byte of the region which initializes the base address register #0
of the S5933 configuration register (Section 3.11). A value of C1h assigns the 16 DWORD
locations of the PCI operation registers into I/O space, a value of C0h defines memory
space, a value of C2h defines memory space below 1 Mbyte.
Required.
Required.
Required.
by an address transfer. Each address/data transfer
consists of 8 bits of information followed by a 1-bit
acknowledgment. When the exchange is complete, a
stop event is issued. Figure 1 shows the unique rela-
tionship defining both a start and stop event. Figure 2
shows the required timing for address/data with
respect to the serial clock.
For random accesses, the sequence involves one
clock to define the start of the sequence, eight clocks
to send the slave address and read/write command,
followed by a one-clock acknowledge, and so on. Fig-
ure 3 shows the sequence for a random write access
requiring 29 serial clock transitions. At the clock speed
for the S5935, this corresponds to one byte of data
transferred approximately every 0.5 milliseconds.
Read accesses may be either random or sequential.
Random read access requires a dummy write to load
the word address and require 39 serial clock transi-
tions. Figure 4 shows the sequence for a random byte
read.
To initialize the S5935 controller’s PCI Configuration
Registers, the smallest serial device necessary is a
128 x 8 organization. Although the S5935 controller
only requires 64 bytes, these bytes must begin at a 64-
byte address offset (0040h through 007Fh). This offset
constraint permits the configuration image to be
shared with a memory containing expansion BIOS
code and the necessary preamble to identify an
expansion BIOS. The largest serial device which may
be used is 2 Kbytes.
Notes
Revision 1.02 – June 27, 2006
Data Book
DS1527
93