S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet - Page 105

• Manufacturer Part Number: S5935QF
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5935QF

• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5935 – PCI Product
Master-Initiated Termination
Occasionally, a PCI transfer must be terminated by the
initiator. Typically, the initiator terminates a transfer
upon the successful completion of the transfer. Some-
times, the initiator’s bus mastership is relinquished by
the bus arbiter (GNT# is removed), often because
another device requires bus ownership. This is called
initiator preemption and is discussed in later Sections.
When the S5935 is an initiator and does not observe a
DEVSEL# response to its assertion of FRAME#, it ter-
minates the cycle (master abort).
Figure 50. Single Data Phase PCI Bus Write of S5935 Registers (S5935 as Target)
Figure 51. Master-Initiated, Normal Completion (S5935 as either Target or Initiator)
AMCC Confidential and Proprietary
PCI CLOCK
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
TRDY#
DEVSEL#
STOP#
(I)
(I)
(T)
(I)
(I)
(T)
(T)
PCI CLOCK
FRAME #
IRDY#
TRDY#
DEVSEL#
STOP#
BUS COMMAND
1
ADDRESS
(T)
(I)
(I)
(T)
(T)
TRANSFER #1
2
BYTE EN 1
DATA 1
1
DATA
COMPLETION
NORMAL
BYTE EN 2
3
IF BURST
ATTEMPT
DATA 2
Normal Cycle Completion
A successful data transfer occurs when both the initia-
tor and target assert their respective ready signals,
IRDY# and TRDY#. The last data phase is indicated
by the initiator when FRAME# is deasserted during a
data transfer. A normal cycle completion occurred if
the target does not assert STOP#. Figure 6 shows the
signal relationships defining a normal transfer
completion.
PCI BUS INTERFACE S5935
2
NO
DATA
TRANSFERRED
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
45
3
Revision 1.02 – June 27, 2006
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
Data Book
DS1527
6
105