S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet - Page 102

• Manufacturer Part Number: S5935QF
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5935QF

• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5935 – PCI Product
PCI BURST TRANSFERS
The PCI bus, by default, expects burst transfers to be
executed. To successfully perform a burst transfer,
both the initiator and target must order their burst
address sequence in an identical fashion. There are
two different ordering schemes: linear address incre-
menting and 80486 cache line fill sequencing. The
exact ordering scheme for a bus transaction is defined
by the state of the two least significant AD lines during
the address phase. The decoding for these lines is
shown below:
The S5935 supports both the linear and the cache line
burst ordering. When the S5935 controller is an initia-
tor, it always employs a linear ordering.
Some accesses to the S5935 controller (as a target)
can not be burst transfers. For example, the S5935
does not allow burst transfers when accesses are
made to the configuration or operation registers
(including the FIFO as a target). Attempts to perform
burst transfers to these regions cause STOP# to be
asserted during the first data phase. The S5935 com-
pletes the initial data phase successfully, but asserting
STOP# indicates that the next access needs to be a
completely new cycle. Accesses to memory or I/O
Figure 46. Zero Wait State Burst Read PCI Bus Transfer (S5935 as Initiator)
102
AD[1:0]
0 0
0 1
1 0
1 1
DS1527
PCI CLOCK
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
TRDY#
DEVSEL#
Linear sequence
Reserved
Cacheline Wrap Mode
Reserved
(T)
(T)
(I)
(I)
(I)
BUS COMMAND
Burst Order
12
ADDRESS
(I)
BYTE ENABLES (1)
3
DATA (1)
(T)
regions defined by the Base Address Registers 1-4
may be bursts, if desired.
PCI Read Transfers
The S5935 responds to PCI bus memory or I/O read
transfers when it is selected (target). As a PCI bus ini-
tiator, the S5935 controller may also produce PCI bus
memory read operations.
Figure 1 depicts the fastest burst read transfer possi-
ble for the PCI bus. The timings shown in Figure 1 are
representative of the S5935 as a PCI initiator with a
fast, zero-wait-state memory target. The signals driven
by the S5935 during the transfer are FRAME#, C/
BE[3:0]#, and IRDY#. The signals driven by the target
are DEVSEL# and TRDY#. AD[31:0] are driven by
both the target and initiator during read transactions
(only one during any given clock). Clock period 2 is a
required bus turn-around clock which ensures bus
contention between the initiator and target does not
occur.
Targets drive DEVSEL# and TRDY# after the end of
the address phase (boundary of clock periods 1 and 2
of Figure 1). TRDY# is not driven until the target can
provide valid data for the PCI read. When the S5935
becomes the PCI initiator, it attempts to perform sus-
tained zero-wait state burst reads until one of the
following occurs:
•
•
•
•
•
•
The memory target aborts the transfer
PCI bus grant (GNT#) is removed
The PCI to Add-On FIFO becomes full
A higher priority (Add-On to PCI) S5935 trans-
fer is pending (if programmed for priority)
The read transfer byte count reaches zero
Bus mastering is disabled from the Add-On
interface
45
BYTE EN (2)
DATA (2)
(T)
BYTE EN (3)
DATA (3)
(T)
Revision 1.02 – June 27, 2006
AMCC Confidential and Proprietary
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
6
Data Book