S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet - Page 164

• Manufacturer Part Number: S5935QF
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5935QF

• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5935 – PCI Product
164
Clock 0:
Clock 1:
Clock 2:
Clock 3:
Clock 4:
Clock 5:
Clock 6:
Clock 7:
Clock 8:
Clock 9:
Clock 10:
Clock 11:
Clock 12:
Clock 13:
DS1527
PCI address information is stored in the S5935 Pass-Thru Address Register. The PCI address is recognized as
an access to Pass-Thru region 1. PTATN# is asserted by the S5935 to indicate a Pass-Thru access is occurring.
PTBURST# is asserted by the S5935, indicating the current Pass-Thru read is a burst.
Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid
when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2.
PTBURST#
PTNUM[1:0] 01.
PTWR
PTBE[3:0]#
The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and
SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3.
SELECT#, byte enable, and the address inputs remain driven to read the Pass-Thru Data Register at offset
2Ch.
WR# asserted at the rising edge of clock 3 writes DATA 1 into the S5935. PTRDY# asserted at the rising edge
of clock 3 completes the current data phase.
Add-On logic drives DATA 2 on the Add-On bus, but PTRDY# deasserted at the rising edge of clock 4 extends
the current data phase.
WR# asserted at the rising edge of clock 5 writes DATA 2 into the S5935. PTRDY# asserted at the rising edge
of clock 5 completes the current data phase.
Add-On logic drives DATA 3 on the Add-On bus, but PTRDY# deasserted at the rising edge of clock 6 extends
the current data phase.
WR# asserted at the rising edge of clock 7 writes DATA 3 into the S5935. PTRDY# asserted at the rising edge
of clock 7 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to
be deasserted. This is how a PCI initiator adds wait states, if it cannot read data quickly enough.
PTATN# remains deasserted at the rising edge of clock 8. The Add-On cannot write DATA 4 until PTATN# is
asserted. Add-On logic continues to drive DATA 4 on the Add-On bus. PTATN# is reasserted during the cycle,
indicating the PCI initiator is done adding wait states.
WR# asserted at the rising edge of clock 9 writes DATA 4 into the S5935. PTRDY# asserted at the rising edge
of clock 9 completes the current data phase.
Add-On logic drives DATA 5 on the Add-On bus, but PTRDY# deasserted at the rising edge of clock 10 extends
the current data phase.
PTATN# remains deasserted at the rising edge of clock 11. The Add-On does not have to write DATA 5 until
PTATN# is asserted. Add-On logic continues to drive DATA 5 on the Add-On bus. PTATN# is reasserted during
the cycle, indicating the PCI initiator is done adding wait states.
PTRDY# asserted at the rising edge of clock 12 completes the final data phase. Any data written into the Pass-
Thru data register is not required and is never passed to the PCI interface (as PTRDY# is not asserted at the ris-
ing edge of clock 13).
PTATN# and PTBURST# deasserted at the rising edge of clock 13 indicates the Pass-Thru access is complete.
The S5935 can accept new Pass-Thru accesses from the PCI bus at clock 14.
Deasserted, the S5935 does not yet recognize a PCI burst.
Indicates the PCI access is to Pass-Thru region 1.
Deasserted. The Pass-Thru access is a read.
0h. Indicate the Pass-Thru access is 32-bits.
Revision 1.02 – June 27, 2006
AMCC Confidential and Proprietary
Data Book