S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet - Page 151

• Manufacturer Part Number: S5935QF
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5935QF

• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5935 – PCI Product
Pass-Thru Status/Control Signals
The S5935 Pass-Thru registers are accessed using
the standard Add-On register access pins. The Pass-
Thru Address Register (APTA) can, optionally, be
accessed using a single, direct access input, PTADR#.
Pass-Thru cycle status indicators are provided to con-
trol Add-On logic based on the type of Pass-Thru
access occurring (single cycle, burst, etc.). The follow-
ing signals are provided for Pass-Thru operation:
Pass-Thru Add-On Data Bus Sizing
Many applications require an 8-bit or 16-bit Add-On
bus interface. Pass-Thru regions can be configured to
support bus widths other than 32-bits. Each Pass-Thru
region can be defined, during initialization, as 8, 16-,
or 32-bits. All of the regions do not need to be the
same. This feature allows a simple interface to 8-and
16-bit Add-On devices.
To support alternate Add-On bus widths, the S5935
performs internal data bus steering. This allows the
Add-On interface to assemble and disassemble 32-bit
PCI data using multiple Add-On accesses to the Pass-
Thru Data Register (APTD). The Add-On byte enable
inputs (BE[3:0]#) are used to access the individual
bytes or words within APTD.
AMCC Confidential and Proprietary
PTATN#
PTBURST#
PTNUM[1:0]
PTBE[3:0]#
PTWR
PTADR#
PTRDY#
BPCLK
Signal
This output indicates a Pass-Thru access
is occurring
This output indicates the Pass-Thru
access is a PCI burst access
These outputs indicate which Pass-Thru
region decoded the PCI address
These outputs indicate which data bytes
are valid (PCI writes), or requested (PCI
reads)
This output indicates if the Pass-Thru
access is a PCI read or a write
When asserted, this input drives the
Pass-Thru Address Register contents
onto the Add-On data bus
When asserted, this input indicates the
current Pass-Thru transfer has been com-
pleted by the Add-On
Buffered PCI bus clock output (to syn-
chronize Pass-Thru data register
accesses)
Function
BUS INTERFACE
The Pass-Thru interface on the S5935 is a PCI target-
only function. Pass-Thru operation allows PCI initia-
tors to read or write resources on the Add-On card. A
PCI initiator may access the Add-On with single data
phase cycles or multiple data phase bursts.
The Add-On interface implements Pass-Thru status
and control signals used by logic to complete data
transfers initiated by the PCI bus. The Pass-Thru inter-
face is designed to allow Add-On logic to function with-
out knowledge of PCI bus activity. Add-On logic only
needs to react to the Pass-Thru status outputs. The
S5935 PCI interface independently interacts with the
PCI initiator to control data flow between the devices.
The following sections describe the PCI and Add-On
bus interfaces. The PCI interface description provides
a basic overview of how the S5935 interacts with the
PCI bus, and may be useful in system debugging. The
Add-On interface description indicates functions
required by Add-On logic and details the Pass-Thru
handshaking protocol.
PCI Bus Interface
The S5935 decodes all PCI bus cycle addresses. If
the address associated with the current cycle is to one
of S5935 Pass-Thru regions, DEVSEL# is asserted. If
the Pass-Thru logic is currently idle (not busy finishing
a previous Pass-Thru operation), the bus cycle type is
decoded and the Add-On Pass-Thru status outputs
are set to initiate a transfer on the Add-On side. If the
Pass-Thru logic is currently busy completing a previ-
ous access, the S5935 signals a retry to PCI initiator.
The following sections describe the behavior of the
PCI interface for Pass-Thru accesses to the S5935.
Single cycle accesses, burst accesses, and target-ini-
tiated retries are detailed.
PCI Pass-Thru Single Cycle Accesses
Single cycle transfers are the simplest PCI bus trans-
action. Single cycle transfers have an address phase
and a single data phase. The PCI bus transaction
starts when an initiator drives address and command
information onto the PCI bus and asserts FRAME#.
The initiator always deasserts frame before the last
data phase. For single cycle transfers, FRAME# is
only asserted during the address phase (indicating the
first data phase is also the last).
When the S5935 sees FRAME# asserted, it samples
the address and command information to determine if
the bus transaction is intended for it. If the address is
within one of the defined Pass-Thru regions, the
S5935 accepts the transfer (assert DEVSEL#), and
Revision 1.02 – June 27, 2006
Data Book
DS1527
151