S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet - Page 167

• Manufacturer Part Number: S5935QF
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5935QF

• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5935 – PCI Product
Figure 89. Pass-Thru Signals after a Target Requested Retry
Internal byte lane steering may be used whether the
MODE input defines a 16-bit or 32-bit Add-On inter-
face. When a 16-bit Add-On interface is used, the
ADR1 input is used in conjunction with the byte
enables to steer data into the proper APTD register
byte locations.
If MODE defines a 16-bit interface, only 16-bits of
address are driven when PTADR# is asserted. If more
than 16-bits of address are required, the Pass-Thru
A d d r e s s R e g i s t e r ( A PTA ) m u s t b e r e a d w i t h
SELECT#, RD#, byte enable and address inputs. Two
consecutive reads are required to latch all of the
address information (one with ADR1=0, one with
ADR1=1).
Regardless of MODE, various data widths may be
used. For Pass-Thru writes (Add-On APTD reads),
Add-On logic must read the APTD register one byte or
one word at a time (depending on the Add-On bus
width). The internal data bus is steered to the correct
portion of APTD using the BE[3:0]# inputs. Table 1
shows the byte lane steering mechanism used by the
S5935. The BYTEn symbols indicate data bytes in the
Pass-Thru Data Register.
When a read is performed with a BEn# input asserted,
the corresponding PTBEn# output is deasserted. Add-
AMCC Confidential and Proprietary
PTNUM[1:0]
PTBURST#
PTBE[3:0]#
SELECT#
ADR[6:2]
DQ[31:0]
PTRDY#
PTATN#
BE[3:0]#
STOP#
BPCLK
PTWR
RD#
On logic cycles through the byte enables to read the
e n t i r e A P T D r e g i s t e r. O n c e a l l d a t a i s r e a d
(PTBE[3:0]# are deasserted), PTRDY# is asserted by
the Add-On, completing the access.
For Pass-Thru reads (Add-On APTD writes), the bytes
requested by the PCI initiator are indicated by the
P T B E [ 3 : 0 ] # o u t p u t s . A d d - O n l o g i c u s e s t h e
PTBE[3:0]# signals to determine which bytes must be
written (and which bytes have already been written).
For example, a PCI initiator performs a byte Pass-Thru
read from an 8-bit Pass-Thru region with PCI BE2#
asserted. On the Add-On interface, PTBE2# is
asserted, indicating that the PCI initiator requires data
in this byte. Once the Add-On writes APTD, byte 2,
PTBE2# is deasserted, and the Add-On may assert
PTRDY#, completing the cycle.
Table 2 shows how the external Add-On data bus is
steered to the Pass-Thru Data Register bytes. This
mechanism is determined by the Pass-Thru region
bus width defined during initialization (see Section
12.3). The BYTEn symbols indicate data bytes in the
Pass-Thru Data Register. For example, an 8-bit Add-
On write with BE1# asserted results in the data on
DQ[7:0] being steered into BYTE1 of the APTD
register.
2Ch
0h
0h
1
Data
Revision 1.02 – June 27, 2006
Fh
Data Book
DS1527
167