S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet - Page 37

• Manufacturer Part Number: S5935QF
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5935QF

• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5935 – PCI Product
Table 7. PCI Command Register
AMCC Confidential and Proprietary
15:10
0 I/O
Bit
9
8
7
6
5
4
3
2
1
Reserved. Equals all 0’s.
Fast Back-to-Back Enable. The S5935 does not support this function. This bit must be set to zero. This bit is cleared
to a 0 upon RESET#.
System Error Enable. When this bit is set to 1, it permits the S5935 controller to drive the open drain output pin,
SERR#. This bit is cleared to 0 upon RESET#. The SERR# pin driven active normally signifies a parity error on the
address/control bus.
Wait Cycle Enable. This bit controls whether this device does address/data stepping. Since the S5935 controller
never uses stepping, it is hardwired to 0.
Parity Error Enable. This bit, when set to a one, allows this controller to check for parity errors. When a parity error is
detected, the PCI bus signal PERR# is asserted. This bit is cleared (parity testing disabled) upon the assertion of
RESET#.
Palette Snoop Enable. This bit is not supported by the S5935 controller and is hardwired to 0. This feature is used
solely for PCI-based VGA devices.
Memory Write and Invalidate Enable. This bit allows certain Bus Master devices to use the Memory Write and Inval-
idate PCI bus command when set to 1. When set to 0, masters must use the Memory Write command instead. The
S5935 controller does not support this command when operated as a master and therefore it is hardwired to 0.
Special Cycle Enable. Devices which are capable of monitoring special cycles can do so when this bit is set to 1.
The S5935 controller does not monitor (or generate) special cycles and this bit is hardwired to 0.
Bus Master Enable. This bit, when set to a one, allows the S5935 controller to function as a bus master. This bit is
initialized to 0 upon the assertion of signal pin RESET#.
Memory Space Enable. This bit allows the S5935 controller to decode and respond as a target for memory regions
that may be defined in one of the five base address registers. This bit is initialized to 0 upon the assertion of signal
pin RESET#.
Space Enable. This bit allows the S5935 controller to decode and respond as a target to I/O cycles which are to
regions defined by any one of the five base address registers. This bit is initialized to 0 upon the assertion of signal
pin RESET#.
Description
Revision 1.02 – June 27, 2006
Data Book
DS1527
37