S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet - Page 29

• Manufacturer Part Number: S5935QF
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5935QF

• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5935 – PCI Product
Register Access Pins (Continued)
FIFO Access Pins
Pass-Thru Interface Pins
AMCC Confidential and Proprietary
SELECT#
RDEMPTY
PTNUM[1:0]
WRFIFO#
PTBURST#
PTBE[3:0]#
RDFIFO#
Signal
MODE
PTRDY#
Signal
PTATN#
WR#
RD#
Signal
Type
Type
out
in
in
in
in
Type
in
in
out
out
out
out
in
Select for the Add-On interface. This signal must be driven low for any write or read access to the Add-
On interface registers. This signal must be stable during the assertion of command signals WR# or
RD#.
Write strobe. This pin, when asserted in conjunction with the SELECT# pin, causes the writing of one
of the internal registers. The specific register and operand size are identified through address pins
ADR[6:2] and the byte enables, BE[3:0]#.
Read strobe. This pin, when asserted in conjunction with the SELECT# pin, causes the reading of one
of the internal registers. The specific register and operand size are identified through address pins
ADR[6:2] and the byte enables BE[3:0]#.
This pin control whether the S5935 data accesses on the DQ bus are to be 32-bits wide (MODE = low)
or 16-bits wide (MODE = high). When in the 16 bit mode, the signal BE3# is reassigned as the address
signal ADR1.
Write FIFO. This signal provides a method to directly write the FIFO without having to generate the
SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO. Access width is either 32 bits
or 16 bits depending on the data bus size available. This signal is intended for implementing PCI DMA
transfers with the Add-On system.
Read FIFO. This signal provides a method to directly read the FIFO without having to generate the
SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO. Access width is either 32 bits
or 16 bits, depending on the data bus size defined by the MODE pin. This signal is intended for imple-
menting PCI DMA transfers with the Add-On system. WRFULL out Write FIFO full. This pin indicates
whether the Add-On-to-PCI bus FIFO is able to accept more data. This pin is intended to be used to
implement DMA hardware on the Add-On system bus. A logic low output from this pin can be used to
represent a DMA write (Add-On to-PCI FIFO) request.
Read FIFO Empty. This pin indicates whether the read FIFO (PCI-to-Add-On FIFO) contains data.
This pin is intended to be used by the Add-On system to control DMA transfers from the PCI bus to the
Add-On system bus. A logic low from this pin can be used to represent a DMA (PCI-to-Add-On FIFO)
request.
Pass-Thru Attention. This signal identifies that an active PCI bus cycle has been decoded and data
must be read from or written to the Pass-Thru Data Register.
Pass-Thru Burst. This signal identifies PCI bus operations involving the current Pass-Thru cycle as
requesting burst access.
Pass-Thru Ready. This input indicates when Add-On logic has completed a Pass-Thru cycle and
another may be initiated.
Pass-Thru Number. These signals identify which of the four base address registers decoded a Pass-
Thru bus activity. These bits are only meaningful when signal PTATN# is active. A value of 00 corre-
sponds to Base Address Register 1, a value of 01 for Base Address Register 2, and so on.
Pass-Thru Byte Enables. These signals indicate which bytes are requested for a given Pass-Thru
operation. They are valid during the presence of signal PTATN# active.
Description
Description
Description
Revision 1.02 – June 27, 2006
Data Book
DS1527
29