S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet - Page 7

• Manufacturer Part Number: S5935QF
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5935QF

• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5935 – PCI Product
BUS INTERFACE ................................................................................................................................................ 139
CONFIGURATION ............................................................................................................................................... 146
PASS-THRU OVERVIEW .................................................................................................................................... 149
FUNCTIONAL DESCRIPTION ............................................................................................................................ 149
BUS INTERFACE ................................................................................................................................................ 151
CONFIGURATION ............................................................................................................................................... 170
ABSOLUTE MAXIMUM RATINGS ...................................................................................................................... 173
DC CHARACTERISTICS ..................................................................................................................................... 173
AMCC Confidential and Proprietary
PCI Initiated Bus Mastering ........................................................................................................................... 138
Address and Transfer Count Registers ......................................................................................................... 138
Bus Mastering FIFO Management Schemes ................................................................................................ 138
FIFO Bus Master Cycle Priority ..................................................................................................................... 139
FIFO Generated Bus Master Interrupts ......................................................................................................... 139
FIFO PCI Interface (Target Mode) ................................................................................................................. 139
FIFO PCI Interface (Initiator Mode) ............................................................................................................... 140
FIFO PCI Bus Master Reads ......................................................................................................................... 142
FIFO PCI Bus Master Writes ......................................................................................................................... 142
Add-On Bus Interface .................................................................................................................................... 142
Add-On FIFO Register Accesses .................................................................................................................. 142
Add-On FIFO Direct Access Mode ................................................................................................................ 142
Additional Status/Control Signals for Add-On Initiated Bus Mastering .......................................................... 144
FIFO Generated Add-On Interrupts ............................................................................................................... 145
8-Bit and 16-Bit FIFO Add-On Interfaces ...................................................................................................... 145
FIFO Setup During Initialization ..................................................................................................................... 146
FIFO Status and Control Bits ......................................................................................................................... 146
PCI Initiated FIFO Bus Mastering Setup ....................................................................................................... 147
Pass-Thru Transfers ...................................................................................................................................... 150
Pass-Thru Status/Control Signals ................................................................................................................. 151
Pass-Thru Add-On Data Bus Sizing .............................................................................................................. 151
PCI Bus Interface .......................................................................................................................................... 151
PCI Pass-Thru Single Cycle Accesses .......................................................................................................... 151
PCI Pass-Thru Burst Accesses ..................................................................................................................... 152
PCI Retry Conditions ..................................................................................................................................... 152
PCI Write Retries ........................................................................................................................................... 152
PCI Read Retries ........................................................................................................................................... 153
Add-On Bus Interface .................................................................................................................................... 153
Single Cycle Pass-Thru Writes ...................................................................................................................... 153
Single Cycle Pass-Thru Reads ...................................................................................................................... 156
Pass-Thru Burst Writes ................................................................................................................................. 156
Pass-Thru Burst Reads ................................................................................................................................. 161
Add-On Pass-Thru Disconnect Operation ..................................................................................................... 165
8-Bit and 16-Bit Pass-Thru Add-On Bus Interface ......................................................................................... 166
S5935 Base Address Register Definition ...................................................................................................... 170
Creating a Pass-Thru Region ........................................................................................................................ 170
Accessing a Pass-Thru Region ..................................................................................................................... 171
Revision 1.02 – June 27, 2006
Data Book
DS1527
7