S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet
S5935QF
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S5935 PCI Product AMCC Confidential and Proprietary S5935 PCI PRODUCT DATA BOOK Part Number S5935 Revision 1.02 – June 27, 2006 Data Book DS1527 1 ...
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S5935 – PCI Product 2 DS1527 (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book AMCC Confidential and Proprietary ...
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... Applied Micro Circuits Corporation (AMCC), the pre- mier supplier of single chip solutions, has developed the S5935 to solve the problem of interfacing applica- tions to the PCI Local bus while offering support for newer PCI chipsets and operating systems ...
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S5935 – PCI Product FEATURES .............................................................................................................................................................. 3 APPLICATIONS ...................................................................................................................................................... 3 DESCRIPTION ........................................................................................................................................................ 3 TABLE OF CONTENTS .......................................................................................................................................... 4 LIST OF FIGURES .................................................................................................................................................. 9 LIST OF TABLES .................................................................................................................................................. 12 S5935 ARCHITECTURE ....................................................................................................................................... 14 S5935 Register Architecture ............................................................................................................................ 14 PCI Configuration Registers ...
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S5935 – PCI Product PCI CONTROLLED BUS MASTER WRITE TRANSFER COUNT REGISTER (MWTC) ..................................... 63 PCI CONTROLLED BUS MASTER READ ADDRESS REGISTER (MRAR) ....................................................... 64 PCI CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC) ........................................ 65 MAILBOX EMPTY FULL/STATUS REGISTER ...
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S5935 – PCI Product PCI BUS INTERRUPTS ...................................................................................................................................... 114 PCI BUS PARITY ERRORS ................................................................................................................................ 114 ADD-ON BUS INTERFACE ................................................................................................................................. 116 ADD-ON OPERATION REGISTER ACCESSES ................................................................................................ 116 Add-On Interface Signals .............................................................................................................................. 116 System Signals .............................................................................................................................................. 116 Register Access Signals ................................................................................................................................ 116 ...
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S5935 – PCI Product PCI Initiated Bus Mastering ........................................................................................................................... 138 Address and Transfer Count Registers ......................................................................................................... 138 Bus Mastering FIFO Management Schemes ................................................................................................ 138 FIFO Bus Master Cycle Priority ..................................................................................................................... 139 FIFO Generated Bus Master Interrupts ......................................................................................................... 139 BUS INTERFACE ...
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S5935 – PCI Product PCI BUS SIGNALS ............................................................................................................................................. 174 ADD-ON BUS SIGNALS ..................................................................................................................................... 175 AC CHARACTERISTICS ..................................................................................................................................... 176 PCI Bus Timings ............................................................................................................................................ 176 ADD-ON BUS TIMINGS ...................................................................................................................................... 178 Synchronous RDFIFO# Timing ..................................................................................................................... 179 Synchronous WRFIFO# Timing ..................................................................................................................... 180 Asynchronous RD# ...
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S5935 – PCI Product Figure 1. S5935 Block Diagram ............................................................................................................................... 3 Figure 2. ................................................................................................................................................................ 14 Figure 3. ................................................................................................................................................................ 18 Figure 4. ................................................................................................................................................................ 19 Figure 5. ................................................................................................................................................................ 20 Figure 6. S5933 Pin Assignment ........................................................................................................................... 21 Figure 7. S5935 Signal Pins .................................................................................................................................. ...
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S5935 – PCI Product Figure 41. Serial Interface Byte Access — Write ................................................................................................... 94 Figure 42. Serial Interface Byte Access — Read ................................................................................................... 94 Figure 43. PCI AD Bus Definition During a Type 0 Configuration Access ............................................................. 95 Figure 44. ...
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S5935 – PCI Product Figure 82. Single Cycle Pass-Thru Read with PTADR# ...................................................................................... 158 Figure 83. Pass-Thru Burst Write ........................................................................................................................ 158 Figure 84. Pass-Thru Burst Writes Controlled by PTRDY# ................................................................................. 159 Figure 85. Pass-Thru Burst Read ........................................................................................................................ 161 Figure 86. ...
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S5935 – PCI Product Table 1. PCI Configuration Registers .................................................................................................................... 15 Table 2. PCI Operation Registers .......................................................................................................................... 16 Table 3. Add-On Bus Operation Registers ............................................................................................................ 17 Table 4. Configuration Registers ........................................................................................................................... 32 Table 5. Vendor Identification Register .................................................................................................................. 34 Table ...
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S5935 – PCI Product Table 41. Supported PCI Bus Commands ........................................................................................................... 101 Table 42. Target Termination Types .................................................................................................................... 109 Table 43. Possible Combinations of FRAME# and IRDY# .................................................................................. 112 Table 44. Byte Lane Steering for Pass-Thru Data Register Read (PCI ...
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S5935 – PCI Product The S5935 is an off-the-shelf, low-cost, standard prod- uct, which is PCI 2.1 compliant. And, since AMCC is a member of the PCI Special Interest Group, the S5935 has been tested on various manufacturer’s PCI moth- ...
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S5935 – PCI Product PCI Configuration Registers All PCI compliant devices are required to provide a group of Configuration Registers for the host system. These registers are polled during power up initializa- tion and contain specific device and add-in card ...
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S5935 – PCI Product Add-On Bus Operation Registers The third and last register group consists of the Add- On Operation Registers, shown in Table 3. This group of eighteen 32-bit (DWORD) registers is accessible to the Add-On Local bus. These ...
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S5935 – PCI Product The optional nvRAM allows the Add-On card manufac- turer to initialize the S5935 with his specific Vendor ID and Device ID numbers along with desired S5935 operation characteristics. The non-volatile memory feature also provides for the ...
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S5935 – PCI Product Figure 3. 18 DS1527 S5935 PCI MB1 PCI MB2 PCI MB3 PCI MB4 Byte 0 Byte 0 Byte 0 Byte 0 PCI MB1 PCI MB2 PCI MB3 PCI MB4 Byte 1 Byte 1 Byte 1 Byte ...
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S5935 – PCI Product Pass-Thru Operation Pass-Thru operation executes PCI bus cycles in real time with the Add-On bus. This allows the PCI bus to directly read or write to Add-On resources. The S5935 allows the designer to declare up ...
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S5935 – PCI Product Figure 5. 20 DS1527 S5935 Endian Converter ...
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S5935 – PCI Product Figure 6. S5933 Pin Assignment 56 AD0 55 AD1 54 AD2 52 AD3 48 AD4 47 AD5 46 AD6 44 AD7 42 AD8 40 AD9 39 AD10 38 AD11 36 AD12 35 AD13 34 AD14 32 ...
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S5935 – PCI Product 22 DS1527 (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book AMCC Confidential and Proprietary ...
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S5935 – PCI Product Signal Type Definition The following signal type definitions [in, out, t/s, s/t/s and o/d] are taken from Revision 2.1 of the PCI local bus specification. Input is a standard input-only signal. in Totem Pole Output is ...
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S5935 – PCI Product Address and Data Pins — PCI Local Bus Signal Type AD[31:00] t/s Local Bus Address/Data lines. Address and data are multiplexed on the same pins. Each bus opera- tion consists of an address phase followed by ...
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S5935 – PCI Product System Pins — PCI Local Bus Signal Type CLK in Clock. The rising edge of this signal is the reference upon which all other signals are based, with the exception of RST# and the interrupt (IRQA#-). ...
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S5935 – PCI Product Error Reporting Pins — PCI Local Bus Signal Type SERR# o/d System Error. This pin is used for reporting address parity errors, data parity errors on Special Cycle com- mands, or any error condition having a ...
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S5935 – PCI Product NON-VOLATILE MEMORY INTERFACE SIGNALS This signal grouping provides for connection to exter- nal non-volatile memories. Either a serial or byte-wide device may be used. The serial interface shares the read and write control pins used for ...
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S5935 – PCI Product ADD-ON BUS INTERFACE SIGNALS The following sets of signals represent the interface pins available for the Add-On function. There are four Register Access Pins Signal Type DQ[31:00] t/s Datapath DQ0–DQ31. These pins represent the datapath for ...
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S5935 – PCI Product Register Access Pins (Continued) Signal Type SELECT# in Select for the Add-On interface. This signal must be driven low for any write or read access to the Add- On interface registers. This signal must be stable ...
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S5935 – PCI Product Pass-Thru Interface Pins Signal Type PTADR# in Pass-Thru Address. This signal causes the actual Pass-Thru requested address to be presented as outputs on the DQ pins DQ[31:0] for Add-Ons with 32-bit buses, or the low-order 16 ...
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S5935 – PCI Product AMCC Confidential and Proprietary (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book DS1527 31 ...
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S5935 – PCI Product PCI CONFIGURATION REGISTERS Each PCI bus device contains a unique 256-byte region called its configuration header space. Portions of this configuration header are mandatory in order for a PCI agent full compliance with ...
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S5935 – PCI Product PCI Configuration Space Header DEVICE ID STATUS BIST MAX_LAT LEGEND EPROM IS DATA SOURCE (READ ONLY) CONTROL FUNCTION EPROM INITIALIZED RAM (CAN BE ALTERED FROM PCI PORT) EPROM INITIALIZED RAM (CAN BE ALTERED ...
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S5935 – PCI Product VENDOR IDENTIFICATION REGISTER (VID) Vendor Identification Register Name 00h-01h Address Offset 10E8h (AMCC, Applied Micro Cir- Power-up value cuits Corp.) External nvRAM offset 040h-41h Boot-load Read Only (RO) Attribute 16 bits Size Figure 8. Vendor Identification ...
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S5935 – PCI Product DEVICE IDENTIFICATION REGISTER (DID) Device Identification Register Name 02h-03h Address Offset 4750h (ASCII hex for ‘GP’, General Power-up value Purpose) External nvRAM offset 042h-43h Boot-load Read Only Attribute 16 bits Size Figure 9. Device Identification Register ...
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S5935 – PCI Product PCI COMMAND REGISTER (PCICMD) PCI Command Register Name 04h-05h Address Offset 0000h Power-up value not used Boot-load Read/Write (R bits, Read Attribute Only for all others) 16 bits Size Figure 10. PCI Command Register ...
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S5935 – PCI Product Table 7. PCI Command Register Bit 15:10 Reserved. Equals all 0’s. 9 Fast Back-to-Back Enable. The S5935 does not support this function. This bit must be set to zero. This bit is cleared ...
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S5935 – PCI Product PCI STATUS REGISTER (PCISTS) PCI Status Register Name 06h-07h Address Offset 0080h Power-up value not used Boot-load Read Only (RO), Read/Write Clear Attribute (R/WC) 16 bits Size Figure 11. PCI Status Register ...
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S5935 – PCI Product Table 8. PCI Status Register Bit 15 Detected Parity Error. This bit is set whenever a parity error is detected. It functions independently from the state of Command Register Bit 6. This bit may be cleared ...
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S5935 – PCI Product REVISION IDENTIFICATION REGISTER (RID) Revision Identification Register Name 08h Address Offset 00h Power-up value External nvRAM/EPROM offset 048h Boot-load Read Only Attribute 8 bits Size Figure 12. Revision Identification Register 7 Table 9. Revision Identification Register ...
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S5935 – PCI Product CLASS CODE REGISTER (CLCD) Class Code Register Name 09h-0Bh Address Offset FF0000h Power-up value External nvRAM offset 049h-4Bh Boot-load Read Only Attribute 24 bits Size Figure 13. @0Bh 7 Base Class Table 10. Defined Base Class ...
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S5935 – PCI Product Table 11. Base Class Code 00h: Early, Pre-2.0 Specification Devices Sub-Class 00h 01h Table 12. Base Class Code 01h: Mass Storage Controllers Sub-Class 00h 01h 02h 03h 04h 80h Table 13. Base Class Code 02h: Network ...
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S5935 – PCI Product Table 17. Base Class Code 06h: Bridge Devices Sub-Class 00h 01h 02h 03h 04h 05h 06h 07h 80h Table 18. Base Class Code 07h: Simple Communications Controllers Sub-Class 00h 01h 80h Table 19. Base Class Code ...
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S5935 – PCI Product Table 21. Base Class Code 0Ah: Docking Stations Sub-Class 00h 80h Table 22. Base Class Code 0Bh: Processors Sub-Class 00h 01h 02h 10h 40h Table 23. Base Class Code 0Ch: Serial Bus Controllers Sub-Class 00 01h ...
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S5935 – PCI Product CACHE LINE SIZE REGISTER (CALN) Cache Line Size Register Name 0Ch Address Offset 00h, hardwired Power-up value not used Boot-load Read Only Attribute 8 bits Size Figure 14. Cache Line Size Register 7 AMCC Confidential and ...
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S5935 – PCI Product LATENCY TIMER REGISTER (LAT) Latency Timer Register Name 0Dh Address Offset 00h Power-up value External nvRAM offset 04Dh Boot-load Read/Write, bits 7:3; Read Only bits Attribute 2:0 8 bits Size Figure 15. Latency Timer Register 7 ...
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S5935 – PCI Product HEADER TYPE REGISTER (HDR) Header Type Register Name 0Eh Address Offset 00h Power-up value External nvRAM offset 04Eh Boot-load Read Only Attribute 8 bits Size Figure 16. Header Type Register AMCC Confidential and ...
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S5935 – PCI Product BUILT-IN SELF-TEST REGISTER (BIST) Built-in Self-Test Register Name 0Fh Address Offset 00h Power-up value External nvRAM/EPROM offset 04Fh Boot-load D7, D5-0 Read Only PCI bus Attribute write only 8 bits Size Figure 17. Built-In ...
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S5935 – PCI Product BASE ADDRESS REGISTERS (BADR) Base Address Register Name 10h, 14h, 18h, 1Ch, 20h, 24h Address Offset FFFFFFC1h for offset 10h; Power-up value 00000000h for all others External nvRAM offset 050h, 54h, Boot-load 58h, 5Ch, 60h (BADR0-4) ...
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S5935 – PCI Product Table 25. Base Address Register — Memory (Bit Bit Description 31:4 Base Address Location. These bits are used to position the decoded region in memory space. Only bits which return a 1 after ...
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S5935 – PCI Product Table 26. Read Response (Memory Assigned All-Ones Write Operation to a Base Address Register Response 00000000h none - disabled FFFFFFF0h 16 bytes (4 DWORDs) FFFFFFE0h 32 bytes (8 DWORDs) FFFFFFC0h 64 bytes (16 DWORDs) ...
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S5935 – PCI Product Table 27. Read Response (I/O Assigned All-Ones write Operation to a Base Address Register Response 00000000h none - disabled FFFFFFFDh 4 bytes (1 DWORDs) FFFFFFF9h 8 bytes (2 DWORDs) FFFFFFF1h 16 bytes (4 DWORDs) ...
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S5935 – PCI Product EXPANSION ROM BASE ADDRESS REGISTER (XROM) Expansion ROM Base Address Register Name 30h Address Offset 00000000h Power-up value External nvRAM offset 70h Boot-load bits 31:11, bit 0 Read/Write; bits 10:1 Attribute Read Only 32 bits Size ...
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S5935 – PCI Product Table 29. Read Response to Expansion ROM Base Address Register (after all-ones written) Response 00000000h none - disabled FFFFF801h 2K bytes (512 DWORDs) FFFFF001h 4K bytes (1K DWORDs) FFFFE001h 8K bytes (2K DWORDs) FFFFC001h 16K bytes ...
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S5935 – PCI Product INTERRUPT LINE REGISTER (INTLN) Interrupt Line Register Name 3Ch Address Offset FFh Power-up value External nvRAM offset 7Ch Boot-load Read/Write Attribute 8 bit Size Figure 20. Interrupt Line Register AMCC Confidential and Proprietary ...
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S5935 – PCI Product INTERRUPT PIN REGISTER (INTPIN) Interrupt Pin Register Name 3Dh Address Offset 01h Power-up value External nvRAM offset 7Dh Boot-load Read Only Attribute 8 bits Size Figure 21. Interrupt Pin Register ...
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S5935 – PCI Product MINIMUM GRANT REGISTER (MINGNT) Minimum Grant Register Name 3Eh Address Offset 00h Power-up value External nvRAM offset 7Eh Boot-load Read Only Attribute 8 bits Size Figure 22. Minimum Grant Register AMCC ...
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S5935 – PCI Product MAXIMUM LATENCY REGISTER (MAXLAT) Maximum Latency Register Name 3Fh Address Offset 00h Power-up value External nvRAM offset 7Fh Boot-load Read Only Attribute 8 bits Size Figure 23. Maximum Latency Register ...
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S5935 – PCI Product AMCC Confidential and Proprietary (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book DS1527 59 ...
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S5935 – PCI Product The PCI bus operation registers are mapped as 16 consecutive DWORD registers located at the address space (I/O or memory) specified by the Base Address Register 0. These locations are the primary method of communication between ...
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S5935 – PCI Product OUTGOING MAILBOX REGISTERS (OMB) Outgoing Mailboxes 1-4 Register Names 00h, 04h, 08h, 0Ch PCI Address Offset XXXXXXXXh Power-up value Read/Write Attribute 32 bits Size INCOMING MAILBOX REGISTERS (IMB) Incoming Mailboxes 1-4 Register Names 10h, 14h, 18h, ...
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S5935 – PCI Product PCI CONTROLLED BUS MASTER WRITE ADDRESS REGISTER (MWAR) Master Write Address Register Name 24h PCI Address Offset 00000000h Power-up value Read/Write Attribute 32 bits Size This register is used to establish the PCI address for data ...
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S5935 – PCI Product PCI CONTROLLED BUS MASTER WRITE TRANSFER COUNT REGISTER (MWTC) Master Write Transfer Count Register Name 28h PCI Address Offset 00000000h Power-up value Read/Write Attribute 32 bits Size Figure 25. PCI Controlled Bus Master Write Transfer Count ...
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S5935 – PCI Product PCI CONTROLLED BUS MASTER READ ADDRESS REGISTER (MRAR) Master Read Address Register Name 2Ch PCI Address Offset 00000000h Power-up value Read/Write Attribute 32 bits Size This register is used to establish the PCI address for data ...
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S5935 – PCI Product PCI CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC) Master Read Transfer Count Register Name 30h PCI Address Offset 00000000h Power-up value Read/Write Attribute 32 bits Size Figure 27. PCI Controlled Bus Master Read Transfer Count ...
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S5935 – PCI Product MAILBOX EMPTY FULL/STATUS REGIS- TER (MBEF) Mailbox Empty/Full Status Register Name 34h PCI Address Offset 00000000h Power-up value Read Only Attribute 32 bits Size Figure 28. Mailbox Empty/Full Status Register 31 66 DS1527 This register provides ...
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S5935 – PCI Product Table 31. Mailbox Empty/Full Status Register Bit 31:16 Incoming Mailbox Status. This field indicates which incoming mailbox registers have been written by the Add-On interface but have not yet been read by the PCI bus. Each ...
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S5935 – PCI Product INTERRUPT CONTROL/STATUS REGIS- TER (INTCSR) Interrupt Control and Status Register Name PCI Address 38h Offset 00000000h Power-up value Read/Write (R/W), Read/ Attribute Write_One_Clear (R/WC) 32 bits Size Figure 29. Interrupt Control/Status Register FIFO ...
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S5935 – PCI Product Figure 30. FIFO Management and Endian Control Byte OUTBOUND FIFO PCI ADD-ON DWORD TOGGLE 0 = BYTES 0-3 (DEFAULT BYTE 4-7 (NOTE1) INBOUND FIFO ADD-ON PCI DWORD TOGGLE 0 = BYTES 0-3 (DEFAULT) 1 ...
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S5935 – PCI Product Table 32. Interrupt Control/Status Register Bit 31:24 FIFO and Endian Control. 23 Interrupt asserted. This read only status bit indicates that one or more of the four possible interrupt conditions is present. This bit is nothing ...
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S5935 – PCI Product Table 32. Interrupt Control/Status Register (Continued) Bit 4 Enable outgoing mailbox interrupt. This bit allows a read by the Add-On of the outgoing mailbox register identified by bits 3 through 0 to produce a PCI interface ...
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S5935 – PCI Product MASTER CONTROL/STATUS REGISTER (MCSR) Master Control/Status Register Name PCI Address 3Ch Offset 000000E6h Power-up value Read/Write, Read Only, Write Attribute Only Size32 bits This register provides for overall control of this device used to ...
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S5935 – PCI Product Table 33. Bus Master Control/Status Register Bit 31:29 nvRAM Access Control. This field provides a method for access to the optional external non-volatile memory. Write operations are achieved by a sequence of byte operations involving these ...
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S5935 – PCI Product Table 33. Bus Master Control/Status Register Bit 12 Read versus Write priority. This bit controls the priority of read transfers over write transfers. When set with bit D8 as zero this indicates that ...
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S5935 – PCI Product AMCC Confidential and Proprietary (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book DS1527 75 ...
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S5935 – PCI Product ADD-ON BUS OPERATION REGISTERS The Add-On bus interface provides access to 18 DWORDs (72 bytes) of data, control and status infor- mation. All of these locations are accessed by asserting the Add-On bus chip select pin ...
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S5935 – PCI Product ADD-ON INCOMING MAILBOX REGISTERS (AIMBX) Add-On Incoming Mailboxes Register Names 1-4 00h, 04h, 08h, 0Ch Add-On Address Offset XXXXXXXXh Power-up value Read Only Attribute 32 bits Size ADD-ON OUTGOING MAILBOX REGISTERS (AOMBX) Add-On Outgoing Mailboxes Register ...
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S5935 – PCI Product ADD-ON CONTROLLED BUS MASTER WRITE ADDRESS REGISTER (MWAR) Master Write Address Register Name 24h Add-On Address Offset 00000000h Power-up value Read/Write Attribute 32 bits Size This register is only accessible when Add-On initiated bus mastering is ...
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S5935 – PCI Product ADD-ON PASS-THRU ADDRESS REGISTER (APTA) Register Add-On Pass-Thru Address Name Add-On 28h Address Offset Power-up XXXXXXXXh value Read Only Attribute 32 bits Size ADD-ON PASS-THRU DATA REGISTER (APTD) Add-On Pass-Thru Data Register Name Add-On 2Ch Address ...
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S5935 – PCI Product ADD-ON CONTROLLED BUS MASTER READ ADDRESS REGISTER (MRAR) Master Read Address Register Name Add-On 30h Address Offset 00000000h Power-up value Read/Write Attribute 32 bits Size This register is only accessible when Add-On initiated bus mastering is ...
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S5935 – PCI Product ADD-ON EMPTY/FULL STATUS REGISTER (AMBEF) Add-On Mailbox Empty/Full Status Register Name Add-On 34h Address Offset 00000000h Power-up value Read Only Attribute 32 bits Size Figure 34. Add-On Mailbox Empty/Full Status Register 31 AMCC Confidential and Proprietary ...
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S5935 – PCI Product Table 35. Add-On Mailbox Empty/Full Status Register Bit 31:16 Outgoing Mailbox Status. This field indicates which outgoing mailbox registers have been written by the Add-On bus interface but have not yet been read by the PCI ...
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S5935 – PCI Product ADD-ON INTERRUPT CONTROL/STATUS REGISTER (AINT) Add-On Interrupt Control and Status Register Name Add-On 38h Address Offset 00000000h Power-up value Read/Write, Read/Write_One_Clear Attribute 32 bits Size Figure 35. Add-On Interrupt Control/Status Register Interrupt Status ...
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S5935 – PCI Product Table 36. Interrupt Control/Status Register Bit 31:24 Reserved. Always zero. 23 Interrupt asserted. This read-only status bit indicates that one or more interrupt conditions is present. This bit is nothing more than the ORing of the ...
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S5935 – PCI Product Table 36. Interrupt Control/Status Register (Continued) Bit 3:2 Incoming Mailbox Interrupt Select. This field selects which of the four incoming mailboxes the source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, ...
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S5935 – PCI Product ADD-ON GENERAL CONTROL/STATUS REGISTER (AGCSTS) Add-On General Control and Status Register Name Add-On 3Ch Address Offset 000000F4h (PCI initiated bus master- ing) 00000034h (Add-On initiated bus Power-up value mastering) Read/Write, Read Only, Write Only Attribute 32 ...
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S5935 – PCI Product Table 37. Add-On General Control/Status Register Bit 31:29 nvRAM/EPROM Access Control. This field provides a method for access to the optional, external non-volatile mem- ory. Write operations are achieved by a sequence of byte operations involving ...
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S5935 – PCI Product Table 37. Add-On General Control/Status Register (Continued) Bit 6 PCI to Add-On Transfer Count Equals Zero (RO). This bit as a one signifies that the read transfer count is all zeros. Only when Add-On initiated bus ...
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S5935 – PCI Product ADD-ON CONTROLLED BUS MASTER WRITE TRANSFER COUNT REGISTER (MWTC) Master Write Transfer Count Register Name Add-On 58h Address Offset 00000000h Power-up value Read/Write Attribute 32 bits Size Figure 37. Add-On Controlled Bus Master Write Transfer Count ...
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S5935 – PCI Product ADD-ON CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC) Master Read Transfer Count Register Name Add-On 5Ch Address Offset 00000000h Power-up value Read/Write Attribute 32 bits Size Figure 38. Add-On Controlled Bus Master Read Transfer Count ...
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S5935 – PCI Product AMCC Confidential and Proprietary (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book DS1527 91 ...
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S5935 – PCI Product INITIALIZATION All PCI bus agents and bridges are required to imple- ment PCI Configuration Registers. When multiple PCI devices are present, these registers must be unique to each device in the system. The specified PCI proce- ...
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S5935 – PCI Product Table 38. Valid External Boot Memory Contents Address Data 0040h-41h not FFFFh This is the location that the S5933 PCI Controller will load a customized vendor ID. (FFFFh is an illegal vendor ID.) 0050h C2h, C1h ...
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S5935 – PCI Product Figure 39. Serial Interface Definition of Start and Stop SCL SDA START BIT Figure 40. Serial Interface Clock/Data Relationship SCL SDA Figure 41. Serial Interface Byte Access — Write ADDRESS R T 1010 ...
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S5935 – PCI Product PCI BUS CONFIGURATION CYCLES Cycles beginning with the assertion IDSEL and FRAME# along with the two configuration command states for C/BE[3:0] (configuration read or write) access an individual device’s configuration space. During the address phase of ...
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S5935 – PCI Product Figure 44. Type 0 Configuration Read Cycles 1 PCI CLOCK (I) FRAME # AD [31:0] ADDRESS (I) CONFIG. READ CMD C/BE [3:0]# (I) (I) IRDY# (T) TRDY# IDSEL (I) (T) DEVSEL# SELECT CONDITION Figure 45. Type ...
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S5935 – PCI Product EXPANSION BIOS ROMS This section provides an example of a typical PC-com- patible expansion BIOS ROM. Address offsets 0040h through 007Fh represent the portion of the external nv memory used to boot-load the S5935 controller. Whether ...
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S5935 – PCI Product Table 39. PC Compatible Expansion ROM Byte Offset Byte Length 68h 8 not used 70h 4 [Expansion ROM base addr.] 74h 8 not used 7Ch 1 [Interrupt line] 7Dh 1 [Interrupt pin] 7Eh 1 [Min-Grant] 7Fh ...
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S5935 – PCI Product AMCC Confidential and Proprietary (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book DS1527 99 ...
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S5935 – PCI Product PCI BUS INTERFACE This section describes the various events which occur on the S5935 PCI bus interface. Since the S5935 con- troller functions as both a target (slave) and an initiator (master), signal timing detail is ...
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S5935 – PCI Product Table 41. Supported PCI Bus Commands C/BE[3:0]# 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read ...
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S5935 – PCI Product PCI BURST TRANSFERS The PCI bus, by default, expects burst transfers to be executed. To successfully perform a burst transfer, both the initiator and target must order their burst address sequence in an identical fashion. There ...
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S5935 – PCI Product Read accesses from the S5935 operation registers (S5935 as a target) are shown in Figure 2. The S5935 conditionally asserts STOP# in clock period 3 if the ini- tiator keeps FRAME# asserted during clock period 2 ...
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S5935 – PCI Product PCI Write Transfers Write transfers on the PCI bus are one clock period shorter than read transfers. This is because the AD[31:0] bus does not require a turn-around cycle between the address and data phases. When ...
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S5935 – PCI Product Master-Initiated Termination Occasionally, a PCI transfer must be terminated by the initiator. Typically, the initiator terminates a transfer upon the successful completion of the transfer. Some- times, the initiator’s bus mastership is relinquished by the bus ...
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S5935 – PCI Product Initiator Preemption A PCI initiator (bus master) is said to be preempted when the system platform deasserts the initiator’s bus grant signal, GNT#, while it still requests the bus (REQ# asserted). This situation occurs if the ...
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S5935 – PCI Product Master Abort PCI accesses to nonexistent or disabled targets never observe DEVSEL# being asserted. In this situation necessary for the initiator to abort the transaction (master abort initiator, S5935 waits for six ...
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S5935 – PCI Product Target Disconnects There are many situations where a target may discon- nect. Slow responding targets may disconnect to permit more efficient (faster) devices to be accessed while they prepare for the next data phase ...
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S5935 – PCI Product Target Requested Retries When the S5935 FIFO registers are accessed (S5935 as a target) and data is unavailable (empty FIFO) for read transfers or cannot be accepted for write trans- fers (full FIFO), the S5935 immediately ...
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S5935 – PCI Product Figure 57. Target Abort Example PCI CLOCK (I) FRAME # (I) IRDY# (T) TRDY# (T) STOP# (T) DEVSEL# Figure 58. PCI Bus Arbitration and S5935 Bus Ownership Example 2 1 S5933 REQ# "OTHER" REQ# S5933 GNT# ...
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S5935 – PCI Product PCI BUS MASTERSHIP When the S5935 requires PCI bus mastership, it pre- sents a request via the REQ# signal. This signal is connected to the system’s PCI bus arbiter. Only one initiator (bus master) may control ...
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S5935 – PCI Product Bus Acquisition Once GNT# is asserted, giving bus ownership to the S5935, the S5935 must wait until the PCI bus becomes idle. This delay is called bus acquisition latency and involves the state of the signals ...
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S5935 – PCI Product Targets selected with LOCK# deasserted during the assertion of FRAME# (clock period 1 of Figure 15), which encounter the assertion of LOCK# during the following clock (clock period 2 of Figure 15) are there- after considered ...
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S5935 – PCI Product PCI BUS INTERRUPTS The S5935 controller is able to generate PCI bus inter- rupts by asserting the PCI bus interrupt signal (INTA#). INTA multisourced, wire-ORed signal on the PCI bus and is driven by ...
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S5935 – PCI Product Figure 63. Error Reporting Signals 12 PCI CLOCK (I) FRAME (I) ADDR A AD[31:0] (I) CMD AA C/BE[3:0]# (T) PAR SERR# (T) (T) PERR# READ TRANSACTION AMCC Confidential and Proprietary (T) (I) ...
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S5935 – PCI Product ADD-ON BUS INTERFACE This chapter describes the Add-On bus interface for the S5935. The S5935 is designed to support connec- tion to a variety of microprocessor buses and/or peripheral devices. The Add-On interface controls S5935 operation ...
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S5935 – PCI Product Asynchronous Register Accesses For many Add-On applications, Add-On logic does not operate at the PCI bus frequency. This is especially true for Add-Ons implementing a microprocessor, which may be operating at a lower (or higher) fre- ...
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S5935 – PCI Product Figure 64. Asynchronous Add-On Operation Register Read BE[3:0]# ADR[6:2] DQ[31:0] SELECT# RD# Figure 65. Asynchronous Add-On Operation Register Write BE[3:0]# ADR[6:2] DQ[31:0] SELECT# WR# 118 DS1527 Revision 1.02 – June 27, 2006 Valid Byte Enables Valid ...
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S5935 – PCI Product Figure 66. Synchronous FIFO or Pass-Thru Data Register Read BPCLK ADR[6:2] Valid 1 BE[3:0]# DQ[31:0] RD# RDFIFO# SELECT# Figure 67. Synchronous FIFO or Pass-Thru Data Register Write BPCLK ADR[6:2] Valid 1 BE[3:0]# DQ[31:0] Valid Data In ...
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S5935 – PCI Product Mailbox Interrupts Mailboxes can be configured to generate Add-On interrupts (IRQ#) and/or allow the Add-On to generate PCI interrupts (INTA#). Mailbox empty/full status con- ditions be can used to interrupt the Add-On or PCI host to ...
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S5935 – PCI Product SELECT#, BE[3:0]#, and ADR[6:2]. RD# and WR# must be deasserted when PTADR# is asserted, but SELECT# may be asserted. These inputs automati- cally drive the address (internally) to 28h and assert all byte enables. The ADR[6:2] ...
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S5935 – PCI Product For the examples below, we will assume the S5935 is I/O mapped with a base address of FC00h. These This example will write 1 byte from NVRAM location 0040h and read it back: In FC00h + ...
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S5935 – PCI Product This example will read 1 byte from NVRAM location 0040h: In FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy). Out FC00h + 3Fh an 80h (CMD to load the ...
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S5935 – PCI Product nv Memory Device Timing Requirements For serial nv memory devices, the serial clock output frequency is the PCI clock frequency divided by 512. This is approximately 65 KHz (with a 33 MHz PCI clock). Any serial ...
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S5935 – PCI Product Memory Device Requirements for Write Accesses Timing Write cycle time Address valid to write active Data valid to write inactive Data hold from write inactive Write pulse width Write inactive Figure 69. nv Memory Write Operation ...
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S5935 – PCI Product MAILBOX OVERVIEW The S5935 has eight 32-bit mailbox registers. The mailboxes are useful for passing command and status information between the Add-On and the PCI bus. The PCI interface has four incoming mailboxes (Add-On to PCI) ...
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S5935 – PCI Product Mailbox Empty/Full Conditions The PCI and Add-On interfaces each have a mailbox status register. The PCI Mailbox Empty/Full Status (MBEF) and Add-On Mailbox Empty/Full Status (AMBEF) Registers indicate the status of all bytes within the mailbox ...
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S5935 – PCI Product to generate a PCI interrupt. The pins are redefined as follows: Signal Pin Add-On Outgoing Mailbox EA0/EMB0 Mailbox 4, bit 24 EA1/EMB1 Mailbox 4, bit 25 EA2/EMB2 Mailbox 4, bit 26 EA3/EMB3 Mailbox 4, bit 27 ...
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S5935 – PCI Product writing the mailbox registers may access all mailbox bytes by cycling through the Add-On byte enable inputs. A similar solution applies to 16-bit Add-On buses. This solution works for Add-Ons which always use just 8-bit or ...
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S5935 – PCI Product Mailbox operations for the Add-On interface are functionally identical. The following sequences are suggested for Add-On mailbox operations using status polling (interrupts disabled): Reading an Add-On Incoming Mailbox: 1. Check Mailbox Status. Read the mailbox status ...
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S5935 – PCI Product Enabling Add-On mailbox interrupts: 1. Enable Add-On outgoing mailbox interrupts. A specific byte within one of the outgoing mailboxes is identified to assert IRQ# when read by the PCI interface. AINT Bit 12 AINT Bits 11:10 ...
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S5935 – PCI Product 1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5935. The interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). AINT Bit 16 AINT Bit ...
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S5935 – PCI Product AMCC Confidential and Proprietary (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book DS1527 133 ...
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S5935 – PCI Product FIFO OVERVIEW The S5935 has two internal FIFOs. One FIFO is for PCI bus to Add-On bus, the other FIFO is for Add-On bus to PCI bus transfers. Each of these has eight 32- bit registers. ...
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S5935 – PCI Product The configurable FIFO advance condition may be used to transfer data to and from Add-On interfaces which are not 32-bits wide. For a 16-bit Add-On bus, the Add-On to PCI FIFO advance condition can be set ...
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S5935 – PCI Product 64-Bit Endian Conversion Because the S5935 interfaces to a 32-bit PCI bus, special operation is required to handle 64-bit data endian con- version. Figure 2c shows 64-bit endian conversion. The S5935 must know whether the lower ...
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S5935 – PCI Product Add-On FIFO Status Indicators The Add-On interface implements FIFO status pins to indicate the full and empty conditions of the PCI to Add-On and Add-On to PCI FIFOs. These may be used by the Add-On to ...
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S5935 – PCI Product For bus master transfers initiated by the Add-On inter- face, some applications may not know the size of the data block to be transferred. To avoid constantly updating the transfer count register, the transfer count may ...
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S5935 – PCI Product the management scheme and finishes transferring the data. The second case is when the S5935 is config- ured for Add-On initiated bus mastering with transfer counts disabled. In this situation, the FIFO manage- ment scheme must ...
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S5935 – PCI Product FIFO PCI Interface (Initiator Mode) The S5935 can act as an initiator on the PCI bus. This allows the device to gain control of the PCI bus to transfer data to or from the FIFO. Internal ...
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S5935 – PCI Product Figure 76. PCI Write to an Empty S5935 FIFO PCI Signals PCI_CLK FRAME# AD[31:0] IRDY# TRDY# DEVSEL# STOP# Add-on Signals RDEMPTY FRF Figure 77. PCI Write to a Full S5935 FIFO (Target Disconnect) PCI Signals PCI_CLK ...
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S5935 – PCI Product FIFO PCI Bus Master Reads For PCI read transfers (filling the PCI to Add-On FIFO), read cycles are performed until one of the fol- lowing occurs: - Bus Master Read Transfer Count Register (MRTC), if used, ...
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S5935 – PCI Product the FIFO condition after it advances, and are updated off of the rising edge of BPCLK. When RDFIFO# is deasserted, the DQ bus floats. The next time RDFIFO# is asserted, data 2 is presented on the ...
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S5935 – PCI Product Additional Status/Control Signals for Add-On Initi- ated Bus Mastering If a serial non-volatile memory is used to configure the S5935, and the device is configured for Add-On initi- ated bus mastering, two additional FIFO status signals ...
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S5935 – PCI Product The FRC# and FWC# inputs allow Add-On logic to reset the PCI to Add-On or Add-On to PCI FIFO flags. The FIFO flags can always be reset with software through the Add-On General Control/Status Register (AGCSTS) ...
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S5935 – PCI Product Some applications hold the RDFIFO# and WRFIFO# inputs active for a synchronous interface. In 16-bit mode, designs must avoid writing to a full FIFO. The data for the write is lost, but the internal mechanism to ...
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S5935 – PCI Product The Add-On General Control/Status (AGCSTS) Add- On Operation Register allows an Add-On CPU to mon- itor FIFO activity and control FIFO operation. Reset controls allow the PCI to Add-On FIFO and Add-On to PCI FIFO flags ...
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S5935 – PCI Product 7. Enable Bus Mastering. Once steps 1-6 are com- pleted, the FIFO may operate as a PCI bus master. Read and write bus master operation may be independently enabled or disabled. MCSR Bit 14 Enable PCI ...
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S5935 – PCI Product 5. Define PCI to Add-On and Add-On to PCI FIFO priority. These bits determine which FIFO has pri- ority if both meet the defined condition to request the PCI bus. If these bits are the same, ...
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S5935 – PCI Product Thru Address Register (APTA), and a Pass-Thru Data Register (APTD). These registers are connected to both the PCI bus interface and the Add-On bus inter- face. This allows a PCI initiator to perform Pass-Thru writes (data ...
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S5935 – PCI Product Pass-Thru Status/Control Signals The S5935 Pass-Thru registers are accessed using the standard Add-On register access pins. The Pass- Thru Address Register (APTA) can, optionally, be accessed using a single, direct access input, PTADR#. Pass-Thru cycle status ...
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S5935 – PCI Product stores the PCI address in the Pass-Thru Address Reg- ister (APTA). For Pass-Thru writes, the S5935 responds immedi- ately (asserting TRDY#) and transfers the data from the PCI bus into the Pass-Thru Data Register (APTD). The ...
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S5935 – PCI Product PCI Read Retries When the S5935 requests a retry for a PCI Pass-Thru read, it indicates that the Add-On could not complete the read in the required time. The Pass-Thru data can- not be read by ...
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S5935 – PCI Product The PCI bus cycle address information is stored in the S5935 Pass-Thru Address Register. Clock 0: The PCI address is recognized as a write to Pass-Thru region 1. The PCI data is stored in the S5935 ...
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S5935 – PCI Product The Add-On PTADR# input directly accesses the Pass-Thru Address Register and drives the contents onto the data bus (no BPCLK rising edge is required). The PCI bus cycle address is stored in the S5935 Pass-Thru Address ...
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S5935 – PCI Product Single Cycle Pass-Thru Reads A single cycle Pass-Thru read operation occurs when a PCI initiator reads a single value from a Pass-Thru region. PCI single cycle transfers consists of an address phase and a one data ...
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S5935 – PCI Product PCI address information is stored in the S5935 Pass-Thru Address Register. Clock 0: The PCI address is recognized as an access to Pass-Thru region 1. PCI data for the first data phase is stored in Clock ...
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S5935 – PCI Product Figure 82. Single Cycle Pass-Thru Read with PTADR# 012345 BPCLK PTATN# PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# SELECT# ADR[6:2] BE[3:0]# WR# DQ[31:0] PTRDY# PTADR# Figure 83. Pass-Thru Burst Write Figure 5 also shows a 5 data phase Pass-Thru ...
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S5935 – PCI Product Figure 84. Pass-Thru Burst Writes Controlled by PTRDY# AMCC Confidential and Proprietary Revision 1.02 – June 27, 2006 Data Book DS1527 159 ...
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S5935 – PCI Product PCI address information is stored in the S5935 Pass-Thru Address Register. Clock 0: The PCI address is recognized as an access to Pass-Thru region 1. PCI data for the first data phase is stored Clock 1: ...
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S5935 – PCI Product Pass-Thru Burst Reads A Pass-Thru burst read operation occurs when a PCI initiator reads multiple DWORDs from a Pass-Thru region. A burst transfer consists of a single address and a multiple data phases. During the address ...
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S5935 – PCI Product PCI address information is stored in the S5935 Pass-Thru Address Register. The PCI address is recognized as Clock 0: an access to Pass-Thru region 1. PTATN# is asserted by the S5935 to indicate a Pass-Thru access ...
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S5935 – PCI Product Figure 7 also shows a 5 data phase Pass-Thru burst read, but the Add-On logic uses PTRDY# to control the rate at which data is transferred. In many applica- tions, Add-On logic is not fast enough ...
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S5935 – PCI Product PCI address information is stored in the S5935 Pass-Thru Address Register. The PCI address is recognized as Clock 0: an access to Pass-Thru region 1. PTATN# is asserted by the S5935 to indicate a Pass-Thru access ...
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S5935 – PCI Product Add-On Pass-Thru Disconnect Operation Slow PCI targets are prevented from degrading PCI bus performance. The PCI specification allows only 16 clocks for a target to respond before it must request a retry on single data phase ...
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S5935 – PCI Product Figure 88. Target Requested Retry after the First Data Phase of a Burst Operation PCICLK FRAME# STOP# BPCLK PTATN# PTRDY# PCI Data Transfer The previous data phase is completed with the asser- tion of PTRDY# at ...
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S5935 – PCI Product Figure 89. Pass-Thru Signals after a Target Requested Retry STOP# BPCLK PTATN# PTBURST# PTNUM[1:0] PTWR PTBE[3:0]# SELECT# ADR[6:2] BE[3:0]# RD# DQ[31:0] PTRDY# Internal byte lane steering may be used whether the MODE input defines a 16-bit ...
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S5935 – PCI Product Table 44. Byte Lane Steering for Pass-Thru Data Register Read (PCI Write) Byte Enables Table 45. ...
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S5935 – PCI Product To write data into the APTD Register, the PTBEn# out- put and the BEn# input must both be asserted. The following describes how APTD Register writes are controlled: Write BYTE3 if PTBE3# AND BE3# are asserted ...
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S5935 – PCI Product CONFIGURATION The S5935 Pass-Thru interface utilizes four Base Address Registers (BADR1:4). Each Base Address Register corresponds to a Pass-Thru region. The con- tents of these registers during initialization determine the characteristics of that particular Pass-Thru region. ...
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S5935 – PCI Product as ones. The number of zeros read back indicates the amount of memory or I/O space a particular S5935 Pass-Thru region is requesting. After the host reads all Base Address Registers in the system (as every ...
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S5935 – PCI Product ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Supply Voltage (VCC) Input Pin Voltage Power Dissipation DC CHARACTERISTICS The Following table summarizes the required parameters defined by the PCI specification as they apply to the S5935 controller. PCI ...
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S5935 – PCI Product PCI BUS SIGNALS The following table summarizes the PCI Bus DC parameters defined by the PCI specification as they apply to the S5935 controller. Signal Type CLK RST# INTA# Open Drain AD[31:0] t/s REQ# t/s GNT# ...
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S5935 – PCI Product ADD-ON BUS SIGNALS Signal Type PCLK IRQ# SYSRST# ADR[6:2] SELECT ADR[6:2] BE[3:0]# RD# WR# DQ[31:0] t/s WRFULL RDEMPTY RDFIFO# WRFIFO# PTATN# PTBURST# PTADR# PTRDY# PTWR PTBE[3:0]# PTNUM[1:0] EQ[7:0] t/s EA[8:0] t/s EA[15:9] MODE TEST FLT# AMCC ...
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S5935 – PCI Product Signal Type ERD#/SCL EWR#/SDA t/s AC CHARACTERISTICS PCI Bus Timings Functional Operation Range (V CC =5.0V ±5%, 0°C to 70° load on outputs) Symbol TCL Cycle Time t1 High Time t2 Low Time t3 ...
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S5935 – PCI Product Figure 92. PCI Output Timing PCI CLK OUTPUT DELAY TRI-STATE OUTPUT Figure 93. PCI Input Timing PCI CLK INPUT AMCC Confidential and Proprietary 1 1.5 1.5 1 Inputs ...
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S5935 – PCI Product ADD-ON BUS TIMINGS Figure 94. Add-On Clock Timing t 1 2.0 Figure 95. Pass-Thru Clock Relationship to PCI Clock PCI CLK BPCLK 178 DS1527 t 2.0 2.0 V IH2 0.8 0 TCL t 10 ...
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S5935 – PCI Product Synchronous RDFIFO# Timing Functional Operation Range (VCC=5.0V 5 Ta’ loaf on outputs). Symbol t RDFIFO# Setup tp BPCLK Rising Edge 144 t RDFIFO# Low Time 145 t RDFIFO# Low ...
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S5935 – PCI Product Synchronous WRFIFO# Timing Functional Operation Range (VCC= 5.0V 5 Ta’ load on outputs). Symbol t WRFIFO# Setup to BPCLK Rising Edge 150 t WRFIFO# Hold Time to BPCLK Rising ...
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S5935 – PCI Product Asynchronous RD# Register Access Timing Functional Operation Range (VCC=5.0V 5 Ta’ load on outputs). Symbol t SELECT# Setup to RD# Rising Edge 110 t SELECT# Hold from RD# Rising ...
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S5935 – PCI Product Asynchronous WR# Register Access Timing Functional Operation Range (VCC=5.0V 5 load on outputs). Symbol t SELECT# Setup to WR# Rising Edge 111 t SELECT# Hold from WR# Rising ...
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S5935 – PCI Product Synchronous RD# FIFO Timing Functional Operation Range (VCC=5.0V 5 load on outputs). Symbol t SELECT# Setup to BPCLK Rising Edge 112 t SELECT# Hold from BPCLK Rising Edge ...
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S5935 – PCI Product Synchronous Multiple RD# FIFO Timing Figure 101. Synchronous RD# FIFO Timing 184 DS1527 Revision 1.02 – June 27, 2006 Data Book AMCC Confidential and Proprietary ...
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S5935 – PCI Product Synchronous WR# FIFO Timing Functional Operation Range (VCC=5.0V 5 Ta’ load on outputs). Symbol t113 SELECT# Setup to BPCLK Rising Edge t113a SELECT# Hold from BPCLK Rising Edge t117 ...
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S5935 – PCI Product Synchronous Multiple WR# FIFO Timing Figure 103. Synchronous Multiple WR# FIFO Timing 186 DS1527 Revision 1.02 – June 27, 2006 Data Book AMCC Confidential and Proprietary ...
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S5935 – PCI Product Target S5935 Pass-Thru Interface Timings Functional Operation Range (VCC=5.0V 5 load on outputs) Symbol t SELECT# Setup to BPCLK Rising Edge 10a t SELECT# Hold from BPCLK Rising Edge ...
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S5935 – PCI Product Figure 104. Pass-Thru Data Register Read Timing BPCLK t 13 ADR[6:2] Valid 1 BE[3:0 DQ[31: RD# SELECT# PTRDY# Figure 105. Pass-Thru Data Register Write Timing BPCLK t 13 ADR[6:2] Valid ...
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S5935 – PCI Product Figure 106. Pass-Thru Status Indicator Timing BPCLK PTATN# PTWR PTBURST# PTNUM[1:0] PTBE[3:0]# Target Byte-Wide nv Memory Interface Timings Functional Operation Range (V CC =5.0V ±5%, 0°C to 70° load on outputs) Symbol t ERD# ...
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S5935 – PCI Product Figure 107. nv Memory Read Timing ERD# (OUTPUT) t EA[15:0] (OUTPUT) EQ[7:0] (INPUT) Figure 108. nv Memory Write Timing EWR# (OUTPUT) EA[15:0] (OUTPUT) EQ[7:0] (OUTPUT) 190 DS1527 Address Valid t 42 ...
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S5935 – PCI Product Target Interrupt Timings Functional Operation Range (V CC =5.0V ±5%, 0°C to 70° load on outputs) Symbol t IRQ# Low from BPCLK Rising Edge 49 t IRQ# High from BPCLK Rising Edge 50 Notes: ...
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S5935 – PCI Product S5935 Pinout and Pin Assignment - 160 PQFP EA10 121 122 PTNUM1 PTNUM0 123 IRQ# 124 DQ19 125 SYSRST# 126 EWR#/SDA 127 ERD#/SCL 128 EA11 129 VSS 130 VCC 131 ADR6 132 DQ18 133 NC 134 ...
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S5935 – PCI Product S5935 Pinout and Pin Assignment - 208 TQFP VDD 157 VSS 158 VSS 159 EA10 160 PTNUM1 161 PTNUM0 162 IRQ# 163 DQ19 164 STSRST# 165 SDA/EWR 166 SCL/ERD 167 N/C 168 EA11 169 VSS 170 ...
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S5935 – PCI Product S5935 Numerical Pin Assign- ment - 160 PQFP Pin# Signal Type 1 EQ0 t/s 2 AD23 t/s 3 AD22 t/s 4 AD21 t/s 5 DQ31 t/s 6 AD20 t/s 7 AD19 t/s 8 AD18 t/s 9 ...
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S5935 – PCI Product Pin# Signal Type 98 DQ2 t/s 99 DQ1 t/s 100 DQ0 t/s 101 EA7 t/s 102 WRFIFO# in 103 WRFULL out 104 RDFIFO# in 105 DQ21 t/s 106 RDEMPTY out 107 PTADR# in 108 PTWR out ...
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S5935 – PCI Product Package Physical Dimensions - 160 PQFP Figure 111. S5935 - 160 PQFP Package Drawing PACKAGE MATERIAL NOTE: Green/RoHS Compliant Package: Lead Finish - MATTE SN. AMCC Confidential and Proprietary Revision 1.02 – June 27, 2006 Data ...
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S5935 – PCI Product Figure 112. S5935 - Marking Drawing LEGEND (in row order - including symbols): ROW #1: AMCC Logo (fixed) ROW #2: AMCC Device Part Number (fixed) ROW #3: S5935: Core Part Number (fixed) UUU: Ordering Options (eg. ...
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S5935 – PCI Product S5935 Numerical Pin Assign- ment - 208 TQFP Pin# Signal Type 1 VDD V 2 VSS V 3 VSS V 4 EQ0 t/s 5 AD23 t/s 6 AD22 t/s 7 AD21 t/s 8 DQ31 t/s 9 ...
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S5935 – PCI Product Pin# Signal Type 98 DQ24 t/s 99 VSS V 100 DQ14 t/s 101 DQ13 t/s 102 DQ12 t/s 103 VDD V 104 VDD V 105 VDD V 106 VSS V 107 VSS V 108 EA4 t/s ...