S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet - Page 24

• Manufacturer Part Number: S5935QF
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5935QF

• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5935 – PCI Product
Address and Data Pins — PCI Local Bus
24
C/BE[3:0]#
AD[31:00]
Signal
PAR
DS1527
Type
t/s
t/s
t/s
Local Bus Address/Data lines. Address and data are multiplexed on the same pins. Each bus opera-
tion consists of an address phase followed by one or more data phases. Address phases are identified
when the control signal, FRAME#, is asserted. Data transfers occur during those clock cycles in which
control signals IRDY# and TRDY# are both asserted.
Bus Command and Byte Enables. These are multiplexed on the same pins. During the address phase
of a bus operation, these pins identify the bus command, as shown in the table below. During the data
phase of a bus operation, these pins are used as Byte Enables, with C/BE[0]# enabling byte 0 (least
significant byte) and C/BE[3]# enabling byte 3 (most significant byte).
Parity. This signal is even parity across the entire AD[31:00] field along with the C/BE[3:0]# field. The
parity is stable in the clock following the address phase and is sourced by the master. During the data
phase for write operations, the bus master sources this signal on the clock following IRDY# active;
during the data phase for read operations, this signal is sourced by the target and is valid on the clock
following TRDY# active. The PAR signal therefore has the same timing as AD[31:00}, delayed by one
clock.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C/BE[3:0]#
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Special Cycle
I/O READ
I/O WRITE
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
MEMORY READ - Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
Description
Description (during address phase)
Revision 1.02 – June 27, 2006
AMCC Confidential and Proprietary
Data Book