S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet - Page 15

• Manufacturer Part Number: S5935QF
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5935QF

• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5935 – PCI Product
PCI Configuration Registers
All PCI compliant devices are required to provide a
group of Configuration Registers for the host system.
These registers are polled during power up initializa-
tion and contain specific device and add-in card
product information including Vendor ID, Device ID,
Revision and the amount of memory required for prod-
uct operation. The S5935 can either load these
registers with default values or initialize them from an
external non-volatile memory area called ‘Configura-
tion Space’. The S5935 can accommodate a total of
256 bytes of external memory for this purpose. The
first 64 bytes is reserved for user defined configuration
data which is loaded into the PCI Configuration Regis-
ters during power-up initialization. The remaining 192
bytes may be used to implement an Expansion BIOS
or contain add-in card POST code. Table 1 shows all
the S5935 PCI Configuration Registers.
PCI Operation Registers
The second group of registers are the PCI Operation
Registers shown in Table 2. This group consists of six-
teen 32-bit (DWORD) registers accessible to the Host
processor from the PCI Local bus. These are the main
registers through which the PCI Host configures
S5935 operation and communicates with the Add-On
Local bus. These registers encompass the PCI bus
incoming and outgoing Mailboxes, FIFO data channel,
Bus Master Address and Count registers, Pass-Thru
data channel registers and S5935 device Status and
Control registers.
AMCC Confidential and Proprietary
Table 1. PCI Configuration Registers
Byte 3
Self Test
Latency
Built-in
Max.
Class Code
PCI Status
Device ID
Expansion ROM Base Address
Min. Grant
Base Address Register 0
Base Address Register 1
Base Address Register 2
Base Address Register 3
Base Address Register 4
Byte 2
Header
Type
Reserved Space
Reserved Space
Reserved Space
Reserved Space
Reserved
Revision 1.02 – June 27, 2006
Byte 1
Interrupt
Latency
Timer
Pin
PCI Command
Revision ID
Vendor ID
Line Size
Byte 0
Interrupt
Cache
Line
Data Book
DS1527
Address
0Ch
1Ch
2Ch
3Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
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