S5935QF Applied Micro Circuits Corporation, S5935QF Datasheet - Page 127

• Manufacturer Part Number: S5935QF
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S5935QF

• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

S5935 – PCI Product
Mailbox Empty/Full Conditions
The PCI and Add-On interfaces each have a mailbox
status register. The PCI Mailbox Empty/Full Status
(MBEF) and Add-On Mailbox Empty/Full Status
(AMBEF) Registers indicate the status of all bytes
within the mailbox registers. A write to an outgoing
mailbox sets the status bits for that mailbox. The byte
enables determine which bytes within the mailbox
become full (and which status bits are set).
An outgoing mailbox for one interface is an incoming
mailbox for the other. Therefore, incoming mailbox sta-
t u s b i ts o n o n e i n t e r f a c e a r e i d e n t i c a l t o t h e
corresponding outgoing mailbox status bits on the
other interface. The following list shows the relation-
ship between the mailbox registers on the PCI and
Add-On interfaces.
A write to an outgoing mailbox also writes data into the
incoming mailbox on the other interface. It also sets
the status bits for the outgoing mailbox and the status
bits for the incoming mailbox on the other interface.
Reading the incoming mailbox clears all correspond-
ing status bits in the Add-On and PCI mailbox status
registers (AMBEF and MBEF).
For example, a PCI write is performed to the PCI out-
going mailbox 2, writing bytes 0 and 1 (BE0# and
BE1# asserted). Reading the PCI Mailbox Empty/Full
Status Register (MBEF) indicates that bits 4 and 5 are
set. These bits indicate that outgoing mailbox 2, bytes
0 and 1 are full. Reading the Add-On Mailbox Empty/
Full Status Register (AMBEF) shows that bits 4 and 5
in this register are also set, indicating Add-On incom-
ing mailbox 2, bytes 0 and 1 are full. An Add-On read
of incoming mailbox 2, bytes 0 and 1 clears the status
bits in both the MBEF and AMBEF status registers.
AMCC Confidential and Proprietary
Outgoing Mailbox1
Outgoing Mailbox 2
Outgoing Mailbox 3
Outgoing Mailbox 4
Incoming Mailbox 1
Incoming Mailbox 2
Incoming Mailbox 3
Incoming Mailbox 4
PCI Mailbox Empty/Full
PCI Interface
=
=
=
=
=
=
=
=
=
Incoming Mailbox 1
Incoming Mailbox 2
Incoming Mailbox 3
Incoming Mailbox 4
Outgoing Mailbox 1
Outgoing Mailbox 2
Outgoing Mailbox 3
Outgoing Mailbox 4
Add-On Mailbox Empty/
Full
Add-On Interface
To reset individual flags in the MBEF and AMBEF reg-
isters, the corresponding byte must be read from the
incoming mailbox. The PCI and Add-On mailbox sta-
tus registers, MBEF and AMBEF, are read-only.
Mailbox flags may be globally reset from either the PCI
interface or the Add-On interface. The PCI Bus Master
Control/Status Register (MCSR) and the Add-On Gen-
eral Control/Status Register (AGCSTS) each have a
bit to reset all of the mailbox status flags.
Mailbox Interrupts
The designer has the option to generate interrupts to
the PCI and Add-On interfaces when specific mailbox
events occur. The PCI and Add-On interfaces can
each define two conditions where interrupts may be
generated. An interrupt can be generated when an
incoming mailbox becomes full and/or when an outgo-
ing mailbox becomes empty. A specific byte within a
specific mailbox is selected to generate the interrupt.
The conditions defined to generate interrupts to the
PCI interface do not have to be the same as the condi-
tions defined for the Add-On interface. Interrupts are
cleared through software.
For incoming mailbox interrupts, when the specified
byte becomes full, an interrupt is generated. The inter-
rupt might be used to indicate command or status
information has been provided, and must be read. For
PCI incoming mailbox interrupts, the S5935 asserts
the PCI interrupt, INTA#. For Add-On incoming mail-
box interrupts, the S5935 asserts the Add-On
interrupt, IRQ#.
For outgoing mailbox interrupts, when the specified
byte becomes empty, an interrupt is generated. The
interrupt might be used to indicate that the other inter-
face has received the last information sent and more
may be written. For PCI outgoing mailbox interrupts,
the S5935 asserts the PCI interrupt, INTA#. For Add-
On outgoing mailbox interrupts, the S5935 asserts the
Add-On interrupt, IRQ#.
Add-On Outgoing Mailbox 4, Byte 3 Access
PCI incoming mailbox 4, byte 3 (Add-On outgoing
mailbox 4, byte 3) does not function exactly like the
other mailbox bytes. When an a serial nv memory boot
device or no external boot device is used, the S5935
pins EA7:0 are redefined to provide direct external
access to Add-On outgoing mailbox 4, byte 3. EA8 is
redefined to provide a load clock which may be used
Revision 1.02 – June 27, 2006
Data Book
DS1527
127