PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 98

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
2.6
2.6.1
The IPAC is programmed via an 8-bit parallel microprocessor interface. Easy and fast
microprocessor access is provided by 8-bit address decoding on the chip.
The IPAC provides three types of P buses (see table 10), which are selected via pin
ALE:
Table 10 Bus Operation Modes
(1)
(2)
(3)
The occurrence of an edge on ALE, either positive or negative, at any time during the
operation immediately selects the interface type (3). A return to one of the other interface
types is possible only if a hardware reset is issued.
Note: If the multiplexed address/data bus type (3) is selected, the unused address pins
Register Addressing Modes
The common way to read write registers is for non-multiplexed mode to set the register
address to the address bus and then access the register location. In multiplexed mode,
the address on the address/data bus is latched in, before a read or write access to the
register is performed.
The IPAC provides two different ways to access its register contents. In the direct mode
the register address to be read or written is directly set on the bus in the way described
above. This mode is selected, if the address select mode pin AMODE is set to 0.
A0-A7 must be tied to V
ALE tied to V
ALE tied to V
Edge on ALE
Microprocessor Interface
Operation Modes
DD
SS
Motorola type with control signals CS, R/W, DS
Siemens/Intel non-multiplexed bus type with control
signals CS, WR, RD
Siemens/Intel multiplexed address/data bus type with
control signals CS, WR, RD, ALE
DD
.
98
Functional Description
PSB 2115
PSF 2115
11.97