PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 72

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
In TE and LT-T mode the IPAC identifies the Q-bit position (after multi-frame
synchronization has been established) by waiting for the F
S/T-interface data stream (F
the Q data will be inserted at the upstream (TE
synchronization is not achieved or lost, it mirrors the received F
Multi-frame synchronization is achieved after two complete multi-frames have been
detected with reference to F
after two or more bit errors in F
sequence, i.e. without a complete valid multi-frame between.
The multi-frame synchronization can be disabled by programming (MFD-bit in MON-8
configuration register).
2.4.4
2.4.4.1
The S/T transceiver of the IPAC PSB 2115 contains four internal registers. Access to
these registers is only possible via the IOM-2 monitor channel. The following registers
are implemented in the IPAC:
• Configuration Register
• Loop-back Register
• IOM-2 Channel Register
• SM/CI Register
The structure of MON-8 write and read request/response commands are shown in the
three tables below:
S/T Transceiver Control
MON-8 Commands (Internal Register Access)
A
/N bit and M bit positions. Multi-frame synchronization is lost
A
[NT
A
/N bit and M bit positions have been detected in
TE] = binary ONE). After successful identification,
72
A
NT) F
bit inversion in the received
Functional Description
A
bits.
A
bit position. When
PSB 2115
PSF 2115
11.97