PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 18

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
1.4
Pin No. Symbol Input (I)
Microprocessor Interface
8
9
10
11
13
14
15
16
18
19
20
21
22
23
24
25
6
5
4
AD0-7
D0...7
A0-A7
RD
DS
WR
R/W
CS
Pin Definitions and Functions
Output (O)
I/O
I/O
I
I
I
I
I
I
Function
Multiplexed Bus Mode:
Address/data bus
Transfers addresses from the host system to the IPAC
and data between the host system and the IPAC.
Non-Multiplexed Bus Mode:
Data bus.
Transfers data between the host system and the IPAC.
Non-Multiplexed Bus Mode:
Address bus transfers addresses from the host system
to the IPAC. For indirect address mode only A0 is valid.
Multiplexed Bus Mode
Not used in multiplexed bus mode. In this case A0-A7
should directly be connected to VDD.
Read
Indicates a read access to the registers (Intel bus
mode).
Data Strobe
The rising edge marks the end of a valid read or write
operation (Motorola bus mode).
Write
Indicates a write access to the registers (Intel bus
mode).
Read/Write
A HIGH identifies a valid host access as a read
operation and a LOW identifies a valid host access as
a write operation (Motorola bus mode).
Chip Select
A LOW on this line selects the IPAC for a read/write
operation.
18
PSB 2115
PSF 2115
Overview
11.97