PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 55

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

The TIC bus is used to control D-channel access on the IOM interface when more than
one HDLC controller is connected. This configuration is illustrated in the above figure for
TE1 where three ICCs are connected to one IOM-2 bus.
On the S bus the D-channel control is handled according to the ITU recommendation
I.430. This control mechanism is required everytime a point to multipoint configuration is
implemented (NT
While the S-bus collision detection is handled by the S interface control of the IPAC, TIC
bus access is mainly controlled by the D-Channel HDLC controller of the IPAC or from
external devices on the IOM-2 interface (e.g. ICC).
The following sections describe both control mechanisms because the TIC bus, although
largely handled by the HDLC controller, represents an important part of D-channel
access.
2.3.4.1
The TIC bus was defined to organize D- and C/I channel access when two or more D-
and C/I channel controllers can access the same IOM-2 timeslot. Bus access is
controlled by five bits in IOM-2 channel No. 2 (see section 2.7.1):
Upstream:
Downstream:
When a controller wants to write to the D or C/I channel the following procedure is
executed:
1. Controller checks whether BAC bit is set to ONE. If this is not the case access
2. The controller transmits its TIC bus address (TBA0…2). This is done in the same
3. After transmitting a TIC bus address bit, the value is read back (with the falling edge)
4. If access was granted, the controller will put the D-channel data onto the IOM-2 bus
Semiconductor Group
currently is not allowed: the controller has to postpone transmission. Only if BAC = 1
the controller may continue with the access procedure.
frame in which BAC = “1” was recognized. On the TIC bus binary “ZERO”s overwrite
binary “ONE”s. Thus low TIC bus addresses have higher priority.
to check whether its own address has been overwritten by a controller with higher
priority. This procedure will continue until all three address bits are sent and
confirmed.
In case a bit is overwritten by an external controller with higher priority, the controller
asking for bus access has to withdraw immediately from the bus by setting all TIC bus
address bits to ONE.
in the following frame provided the S/G bit is set to ZERO (i.e. S-bus free to transmit).
The BAC bit will be set to ZERO by the controller to block all remaining controllers.
In case the S/G bit is ONE this prevents only the D-channel data to be switched
TIC Bus D-Channel Control in TE
TE1 … TE8).
BAC
TBA0 … 2
S/G
55
Bus access control bit
TIC bus address bits 0 … 2
Stop/Go bit
Functional Description
PSB 2115
PSF 2115
11.97