PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 95

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Note: Bit RSS has a significance only if terminal specific functions are activated
Switching RSS from 0 to 1 or from 1 to 0 resets the watchdog timer.
The reset pulse generated by the IPAC (output via RES pin) has a pulse width of 5 ms
and is an active high signal. It has no internal reset function.
Before and after this reset pulse the RES pin is input.
1
The RSS bit should be set to “1” by the user when the IPAC is in power-up to prevent an
edge on the EAW line or a change in the C/I code from generating a reset pulse.
Semiconductor Group
A reset signal is generated as a result of the expiration of the
watchdog timer (indicated by the WOV interrupt status).
Note: The watchdog timer is not running when the IPAC is in the power-down state
(TSF=1).
(IOM not clocked).
95
Functional Description
PSB 2115
PSF 2115
11.97