PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 275

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
TNRX ... Time Slot Number Receive
Selects one of up to 32 possible timeslots (00h-1Fh) in which data is received from the
PCM interface.
Note: The configuration of the PCM timeslots is equal for B1 and B2-channel.
4.4.10
Value after reset: 00
POTA1
POTA2
POTA1 refers to the B1-channel and POTA2 to the B2-channel of the IOM channel which
is selected by PCFG:CSL2-0.
ENA ... Enable PCMOUT channel
0: Disables...
1: Enables ... transmission of data on the PCM interface line PCMOUT.
Note: Data is transmitted by the IPAC on the PCM interface to an external device.
DUDD ... Switch on IOM-2 DU/DD line
The selected PCM timeslot on the PCM interface is mapped to the
0: DD-line (default)
1: DU-line ... of the IOM-2 interface.
SRES... Software Reset
0: Deactivates ...
1: Activates ... the internal RESET state of the IPAC.
The RESET state is activated to the internal blocks of the IPAC when a ’1’ is written to
SRES and it is active until the SRES-bit is set to ’0’ again, i.e. the host must ensure the
required RESET timing of the IPAC which is 4 ms.
This data may be originated from the B1/B2 channel of the IOM-2 DD-line (default)
or DU-line.
POTA1/2 - PCM Output Time Slot Assignment B1/B2 (Read/Write)
7
7
ENA DUDD
ENA DUDD SRES
H
0
275
TNTX
TNTX
Detailed Register Description
0
0
PSB 2115
PSF 2115
11.97
(C9)
(C8)