PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 164

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

read the IPAC interrupt status register (ISTA) in the associated interrupt service routine.
The six lowest order bits (bit 5-0) of ISTA (IDC, EXD, ICA, EXA, ICB, EXB) point to those
registers in which the actual interrupt source is indicated. It is possible that several
interrupt sources are indicated referring to one interrupt request (e.g. if the ICA bit is set,
at least one interrupt is indicated in the ISTA register of channel A).
An interrupt source from the general I/O pins AUX6 and AUX7 of the auxiliary interface
is directly indicated in bits 6 and 7 of the ISTA register, therefore these bits must always
be checked (see chapter 3.3.3).
Two bits indicate an interrupt source from the D-channel (see chapter 3.3.2) and for
each of the channels A and B another two bits indicate a source from ISTAB or EXIRB
(see chapter 3.3.1).
The INT pin of the IPAC remains active until all interrupt sources are cleared by reading
the corresponding interrupt register. Therefore it is possible that the INT pin is still active
when the interrupt service routine is finished.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FF
and write back the old mask to the MASK register.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
The ISTA register represents the combined interrupt status from all the individual
interrupt status registers (ISTAD, EXIRD, ISTAB, EXIRB). If a specific interrupt source
(e.g. ISTAD:RME) is acknowledged by the host the interrupt indication in the ISTA
register (in this case ISTA:ICD) is reset, it does not need to be acknowledged by reading
ISTA.
In other words, the host does not need to read the ISTA register if it uses some other
mechanism to determine the interrupt source. This may be suitable for the adaptation of
driver software based on HSCX-TE PSB 21525 and ISAC-S TE PSB 2186 which already
implements the subsequent check of all B-channel and D-channel interrupt registers.
Two interrupt indications can be read directly from the ISTA register and another six
interrupt indications from separate interrupt status registers and extended interrupt
registers for the B-channels (ISTAB, EXIRB, each for B-Channel A and B) and the D-
channel (ISTAD, EXIRD).
After the IPAC has requested an interrupt by setting its INT pin to low, the host must first
Semiconductor Group
164
Operational Description
H
into the MASK register)
PSB 2115
PSF 2115
11.97