PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 69

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PSB 2115
PSF 2115
Functional Description
2.4.2
S/T-Interface Coding
Transmission over the S/T-interface is performed at a rate of 192 kbit/s. Pseudo-ternary
coding with 100 % pulse width is used (see following section). 144 kbit/s are used for
user data (B1+B2+D), 48 kbit/s are used for framing and maintenance information. The
IPAC uses two symmetrical, differential outputs (SX1, SX2) and two symmetrical,
differential inputs (SR1, SR2). These signals are coupled via external circuitry and two
transformers onto the 4 wire S-interface. The nominal pulse amplitude on the S-interface
is 750 mV (zero-peak).
The following figure illustrates the code used. A binary ONE is represented by no line
signal. Binary ZEROs are coded with alternating positive and negative pulses with two
exceptions:
The first binary ZERO following the framing balance bit is of the same polarity as the
framing-balancing bit (required code violation) and the last binary ZERO before the
framing bit is of the same polarity as the framing bit.
Figure 22
S/T -Interface Line Code (without code violation)
A standard S/T frame consists of 48 bits. In the direction TE
NT the frame is
transmitted with a two bit offset. For details on the framing rules please refer to ITU I.430
section 6.3. The following figure illustrates the standard frame structure for both
directions (NT
TE and TE
NT) with all framing and maintenance bits.
Semiconductor Group
69
11.97