PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 201

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PSB2115FV1.2D

Manufacturer Part Number
PSB2115FV1.2D
Description
Manufacturer
Lantiq
Datasheet

Specifications of PSB2115FV1.2D

Lead Free Status / Rohs Status
Supplier Unconfirmed
PSB 2115
PSF 2115
Operational Description
Reset state
A hardware or software reset (RES) forces the IPAC to an idle state where the analog
components are disabled (transmission of INFO0) and the S/T line awake detector is
inactive. Thus activation from the NT is not possible. Clocks are still supplied and the
outputs are in a low impedance state.
Semiconductor Group
201
11.97

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