PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 157

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
General IPAC registers
The IPAC registers for general functions are located in the address range C0h - CCh.
The reset values are summarized in table 18.
Table 19 RESET Values for General IPAC Registers
Register
CONF
ISTA
MASK
ACFG
AOE
ATX
PITA1/2
POTA1/2
PCFG
SCFG
TIMR2
Value after
Reset (hex)
00
00
C0
00
FC
00
00
00
00
00
00
Meaning
– transformer ratio 2:1
– Test mode disabled
– D-Channel priority handler disabled
– Pin AUX7 is general I/O
– DU/DD are open drain
– IOM is operational
– No interrupts
– INT0/1 masked
– All other interrupts enabled
– AUX2-7 are open drain (as outputs)
– INT0,1 are negative level triggered (as INT inputs)
– AUX2-7 are inputs
– Output value for AUX2-7 is 0
– PCMIN line is disabled
– RX data from PCMIN mapped to DU line
– Selected PCM timeslot is channel 0
– PCMOUT line is disabled
– TX data on PCMOUT derived from DD line
– Selected PCM timeslot is channel 0
– ACL will indicate S-bus activation status
– AUX3-5 are used for PCM interface (LT modes)
– FSC (derived from DCL in) is output
– IOM Channel 0 selected for PCM interface
– 8 bit timeslot length
– SDS active during timeslot 0
– Count down timer mode
– Timer is disabled
on AUX3 (LT modes)
(LT modes)
157
Operational Description
PSB 2115
PSF 2115
11.97