PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 96

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
2.5.9
2.5.9.1
To provide for fast and efficient testing, the IPAC can be operated in the test mode by
setting the TLP bit in the MODEB register.
The serial data input and output (DU – DD) are connected generating a local loopback
between XFIFOB and RFIFOB.
The DD input is ignored and DU remains active.
As a result, the user can perform a simple test of the HDLC channels of the IPAC.
2.5.9.2
The IPAC provides several test and diagnostic functions for D-Channel and S/T interface
which can be grouped as follows:
– digital loop via TLP (Test Loop, SPCR register) command bit (figure 36): TX-path of
Figure 36
– test of layer-2 functions while disabling all layer-1 functions and pins associated with
layer 2 is internally connected with RX-path of layer 2, output from layer 1 (S/T) on DD
is ignored; this is used for testing D-channel functionality excluding layer 1 (loopback
between XFIFOD and RFIFOD) and excluding the B-channel controller;
them (including clocking in TE mode), via bit TEM (Test Mode in CONF register); the
IPAC is then fully compatible to the ICC (PEB 2070) seen at the IOM interface.
Test Functions
B-Channel Test Mode
D-Channel and S/T Interface Test Mode
Layer 2 Test Loops
96
Functional Description
PSB 2115
PSF 2115
11.97