PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 183

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
3.5
3.5.1
After the XFIFOD status has been checked by polling the Transmit FIFO Write Enable
(XFW) bit or after a Transmit Pool Ready (XPR) interrupt, up to 32 bytes may be entered
in XFIFOD. Transmission of an HDLC frame is started when a transmit command is
issued. The opening flag is generated automatically. In the case of an auto mode
transmission (XIF or XIFC), the control field is also generated by the IPAC, and the
contents of register XAD1 (and XAD2 for LAPD) are transmitted as the address, as
shown in figure 87.
Figure 87
* Transmit
* Transmit
Transparent
Frame
I Frame
(auto-mode only!)
Transmitted
HDLC Frame
D-Channel Data Transfer
HDLC Frame Transmission
Transmit Data Flow
Flag
Description of Symbols:
Address
XAD1
High
Generated automatically by IPAC
Written initially by CPU (into register)
Loaded (repeatedly) by CPU upon IPAC request (XPR interrupt)
Address
If 2 byte
address
field
selected
XAD2
Low
183
XFIFOD
Control
INFORMATION
XFIFOD
Operational Description
Appended if CPU
has issued
transmit message
end (XME)
command.
CRC
PSB 2115
PSF 2115
ITD09625
Flag
11.97