PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 240

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.3.6
Value after reset: 00
CMDRD
RMC ... Receive Message Complete
Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By
setting this bit, the processor confirms that it has fetched the data, and indicates that the
corresponding space in the RFIFOD may be released.
RRES ... Receiver Reset
HDLC receiver is reset, the RFIFOD is cleared of any data. In addition, in auto mode, the
transmit and receive counters (V(S), V(R)) are reset.
RNR ... Receiver Not Ready. Used in auto mode only.
Determines the state of the IPAC HDLC receiver.
When RNR = “0”, a received I or S-frame is acknowledged by an RR supervisory frame,
otherwise by an RNR supervisory frame.
STI ... Start Timer
The IPAC hardware timer is started when STI is set to one. In the internal timer mode
(TMD bit, MODED register) an S Command (RR, RNR) with poll bit set is transmitted in
addition. The timer may be stopped by a write to the TIMR1 register.
XTF ... Transmit Transparent Frame
After having written up to 32 bytes in the XFIFOD, the processor initiates the
transmission of a transparent frame by setting this bit to “1”. The opening flag is
automatically added to the message by the IPAC.
XIF ... Transmit I Frame. Used in auto mode only
After having written up to 32 bytes in the XFIFOD, the processor initiates the
transmission of an I frame by setting this bit to “1”. The opening flag, the address and the
control field are automatically added by the IPAC.
Semiconductor Group
CMDRD - Command Register (Write)
7
RMC RRES RNR
H
STI
240
XTF
XIF
Detailed Register Description
XME XRES
0
PSB 2115
PSF 2115
11.97
(A1)