PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 28

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F917/916/914/913
2.2.2.6
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-6.
REGISTER 2-6:
DS41250E-page 26
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIR1 Register
PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)
EEIF: EE Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not started
ADIF: A/D Converter Interrupt Flag bit
1 = The A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is not full
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The Transmission/Reception is complete (must be cleared in software)
0 = Waiting to Transmit/Receive
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
Compare Mode
PWM mode
TMR2IF: TMR2 to PR2 Interrupt Flag bit
1 = A TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow
bit 7
Legend:
R = Readable bit
- n = Value at POR
R/W-0
EEIF
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
Unused in this mode
R/W-0
ADIF
RCIF
R-0
Preliminary
W = Writable bit
‘1’ = Bit is set
TXIF
R-0
Note:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
SSPIF
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
CCP1IF
R/W-0
© 2005 Microchip Technology Inc.
x = Bit is unknown
TMR2IF
R/W-0
TMR1IF
R/W-0
bit 0