PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 183

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 15-5:
A PWM output (Figure 15-6) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 15-6:
15.3.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
PWM frequency is defined as 1/[PWM period].
© 2005 Microchip Technology Inc.
Note 1:
CCPR1H (Slave)
Comparator
CCPR1L
TMR2 = PR2
Duty Cycle Registers
TMR2
PR2
Comparator
Duty Cycle
(TMR2 prescale value)
PWM period = (PR2) + 1] • 4 • T
PWM PERIOD
The 8-bit timer is concatenated with 2-bit internal Q
clock, or 2 bits of the prescaler, to create 10-bit time
base.
Period
(1)
TMR2 = Duty Cycle
Clear Timer,
CCP1 pin and
latch D.C.
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM OUTPUT
TMR2 = PR2
CCP1CON<5:4>
R
S
Q
TRISC<5>
OSC
CCP1/SEG10
RC5/T1CKI/
•
Preliminary
PIC16F917/916/914/913
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The RC5/T1CKI/CCP1/SEG10 pin is set
• The PWM duty cycle is latched from CCPR1L into
15.3.2
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitch-free PWM operation.
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock, or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the formula:
PWM Resolution
(exception: if PWM duty cycle = 0%, the
RC5/T1CKI/CCP1/SEG10 pin will not be set)
CCPR1H
Note:
Note:
T
PWM duty cycle =(CCPR1L:CCP1CON<5:4>) •
OSC
• (TMR2 prescale value)
The Timer2 postscaler (see Section 7.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM DUTY CYCLE
If the PWM duty cycle value is longer than
the
RC5/T1CKI/CCP1/SEG10 pin will not be
cleared.
=
log
---------------------------------------------------------------------------bits
PWM
⎛
⎝
-------------------------------------------------------------
F
PWM
log
TMR2 Prescaler
F
OSC
2
DS41250E-page 181
period,
⎞
⎠
the