PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 265

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Reset................................................................................. 187
Revision History ................................................................ 257
S
S (Start) bit ........................................................................ 160
SCI. See USART
Serial Communication Interface. See USART.
Slave Select Synchronization ........................................... 166
SMP bit ............................................................................. 160
Software Simulator (MPLAB SIM)..................................... 216
Special Function Registers ................................................. 14
SPI Mode .................................................................. 159, 166
SSP
SSP I
SSP Module
© 2005 Microchip Technology Inc.
PIE2 (Peripheral Interrupt Enable 2)........................... 25
PIR1 (Peripheral Interrupt Register 1) ........................ 26
PIR2 (Peripheral Interrupt Register 2) ........................ 27
PORTA........................................................................ 32
PORTB........................................................................ 42
PORTC ....................................................................... 51
PORTD ....................................................................... 60
PORTE........................................................................ 65
RCSTA (Receive Status and Control)....................... 128
Reset Values............................................................. 192
Reset Values (Special Registers) ............................. 194
Special Function Register Map
Special Register Summary
SSPCON (Sync Serial Port Control) Register........... 161
SSPSTAT (Sync Serial Port Status) Register........... 160
Status.......................................................................... 21
T1CON (Timer1 Control)............................................. 87
T2CON (Timer2 Control)............................................. 90
TRISA (PORTA Tri-state) ........................................... 32
TRISB (PORTB Tri-state) ........................................... 42
TRISC (PORTC Tri-state) ........................................... 51
TRISD (PORTD Tri-state) ........................................... 60
TRISE (PORTE Tri-state) ........................................... 65
TXSTA (Transmit Status and Control) ...................... 127
VRCON (Voltage Reference Control) ....................... 100
WDTCON (Watchdog Timer Control) ....................... 200
WPUB (Weak Pull-up PORTB) ................................... 43
Associated Registers ................................................ 168
Bus Mode Compatibility ............................................ 168
Effects of a Reset...................................................... 168
Enabling SPI I/O ....................................................... 164
Master Mode ............................................................. 165
Master/Slave Connection.......................................... 164
Serial Clock (SCK pin) .............................................. 159
Serial Data In (SDI pin) ............................................. 159
Serial Data Out (SDO pin) ........................................ 159
Slave Select .............................................................. 159
Slave Select Synchronization ................................... 166
Sleep Operation ........................................................ 168
SPI Clock .................................................................. 165
Typical Connection ................................................... 164
Overview
SPI Master/Slave Connection ................................... 164
Slave Mode ............................................................... 169
Clock Synchronization and the CKP Bit.................... 175
2
C Operation ............................................................ 169
PIC16F913/916................................................... 15
PIC16F914/917................................................... 16
Bank 0................................................................. 17
Bank 1................................................................. 18
Bank 2................................................................. 19
Bank 3................................................................. 20
Preliminary
PIC16F917/916/914/913
SSPEN bit......................................................................... 161
SSPM bits ......................................................................... 161
SSPOV bit ........................................................................ 161
Status Register ................................................................... 21
Synchronous Master Reception
Synchronous Master Transmission
Synchronous Serial Port Enable bit (SSPEN) .................. 161
Synchronous Serial Port Mode Select bits (SSPM).......... 161
Synchronous Serial Port. See SSP
Synchronous Slave Reception
Synchronous Slave Transmission
T
T1CON Register ................................................................. 87
Time-out Sequence .......................................................... 190
Timer0
Timer0 Module.................................................................... 81
Timer1
Timer1 Module with Gate Control ....................................... 85
Timer2 ................................................................................ 90
Timing Diagrams
SPI Master Mode...................................................... 165
SPI Slave Mode........................................................ 166
SSPBUF ................................................................... 165
SSPSR ..................................................................... 165
Associated Registers................................................ 140
Associated Registers................................................ 139
Associated Registers................................................ 142
Associated Registers................................................ 142
Associated Registers.................................................. 83
External Clock ............................................................ 82
External Clock Requirements ................................... 234
Interrupt ...................................................................... 81
Operation.................................................................... 81
T0CKI ......................................................................... 82
Associated Registers.................................................. 89
Asynchronous Counter Mode ..................................... 88
External Clock Requirements ................................... 234
Interrupt ...................................................................... 86
Modes of Operations .................................................. 86
Operation During Sleep .............................................. 89
Prescaler .................................................................... 86
Resetting of Timer1 Registers .................................... 89
Resetting Timer1 Using a CCP Trigger Output .......... 88
Timer1 Gate
TMR1H Register......................................................... 85
TMR1L Register ......................................................... 85
Associated registers ................................................... 91
Operation.................................................................... 90
Postscaler................................................................... 90
PR2 Register .............................................................. 90
Prescaler .................................................................... 90
TMR2 Output .............................................................. 91
TMR2 Register ........................................................... 90
TMR2 to PR2 Match Interrupt............................... 90, 91
A/D Conversion ........................................................ 243
Asynchronous Master Transmission ........................ 132
Asynchronous Master Transmission (Back to Back) 132
Asynchronous Reception.......................................... 135
Asynchronous Reception with Address Byte First .... 137
Asynchronous Reception with Address Detect......... 137
Brown-out Reset (BOR)............................................ 232
Reading and Writing ........................................... 88
Inverting Gate ..................................................... 86
Selecting Source .......................................... 86, 97
Synchronizing C2OUT w/ Timer1 ....................... 97
DS41250E-page 263