PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 188

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F917/916/914/913
16.1
The configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations as shown in Register 16-1.
These bits are mapped in program memory location
2007h.
REGISTER 16-1:
DS41250E-page 186
bit 13
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
—
DEBUG
Configuration Bits
Unimplemented: Read as ‘1’
DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are dedicated to the debugger
FCMEN: Fail-Safe Clock Monitor Enabled bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switchover mode is disabled
BOREN<1:0>: Brown-out Reset Selection bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit (PCON<4>)
00 = BOR disabled
CPD: Data Code Protection bit
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
MCLRE: RB3/MCLR/V
1 = RB3/MCLR/V
0 = RB3/MCLR/V
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)
FOSC<2:0>: Oscillator Selection bits
111 = RC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI
110 = RCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI
101 = INTOSC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI
100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI
011 = EC: I/O function on RA6/OSC2/CLKO/T1OSO pin, CLKI on RA7/OSC1/CLKI/T1OSI
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI
Legend:
R = Readable bit
- n = Value at POR
Note 1:
FCMEN
2:
3:
4:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire data EEPROM will be erased when the code protection is turned off.
The entire program memory will be erased when the code protection is turned off.
When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
CONFIG – CONFIGURATION WORD (ADDRESS: 2007h)
PP
PP
pin function is MCLR
pin function is digital input, MCLR internally tied to V
IESO
PP
(3)
pin function select bit
BOREN1
(2)
W = Writable bit
‘1’ = Bit is set
BOREN0
(1)
(4)
Preliminary
CPD
CP
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Note:
DD
MCLRE
program memory space. It belongs to the
special
(2000h-3FFFh), which can be accessed
only
“PIC16F917/916/914/913
Programming Specification” (DS41244)
for more information.
Address 2007h is beyond the user
PWRTE
during
configuration
WDTE
© 2005 Microchip Technology Inc.
x = Bit is unknown
FOSC2
programming.
memory
FOSC1
Memory
FOSC0
space
See
bit 0