PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 109

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.3
The LCD driver module can be configured into four
multiplex types:
• Static (only COM0 used)
• 1/2 multiplex (COM0 and COM1 are used)
• 1/3 multiplex (COM0, COM1 and COM2 are used)
• 1/4 multiplex (all COM0, COM1, COM2 and COM3
The LMUX<1:0> setting decides the function of RB5,
RA2 or either RA3 or RD0 pins (see Table 9-1 for
details).
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. If the pin is a COM drive,
then the TRIS setting of that pin is overridden.
TABLE 9-1:
9.4
The LCDSEn registers are used to select the pin
function for each segment pin. The selection allows
each pin to operate as either an LCD segment driver or
as one of the pin’s alternate functions. To configure the
pin as a segment pin, the corresponding bits in the
LCDSEn registers must be set to ‘1’.
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. Any bit set in the LCDSEn
registers overrides any bit settings in the corresponding
TRIS register.
9.5
The LCDDATAx registers contain bits which define the
state of each pixel. Each bit defines one unique pixel.
Register 9-4 shows the correlation of each bit in the
LCDDATAx registers to the respective common and
segment signals.
Any LCD pixel location not being used for display can
be used as general purpose RAM.
© 2005 Microchip Technology Inc.
Note 1:
are used)
Note:
LMUX
Note:
<1:0>
00
01
10
11
LCD Multiplex Types
Segment Enables
Pixel Control
RA3 for PIC16F913/916, RD0 for
PIC16F914/917
COM3 Driver COM2 Driver COM1 Driver
On a Power-on Reset, the LMUX<1:0>
bits are ‘11’.
On a Power-on Reset, these pins are
configured as digital I/O.
RA3/RD0
Digital I/O
Digital I/O
Digital I/O
RA3, RA2, RB5 FUNCTION
(1)
COM2 Driver COM1 Driver
Digital I/O
Digital I/O
RA2
COM1 Driver
Digital I/O
RB5
Preliminary
PIC16F917/916/914/913
9.6
The rate at which the COM and SEG outputs change is
called the LCD frame frequency.
TABLE 9-2:
TABLE 9-3:
Multiplex
Note:
LP<3:0>
Static
1/2
1/3
1/4
2
3
4
5
6
7
LCD Frame Frequency
Clock source is F
LFINTOSC/32.
Clock source/(4 x 1 x (LP<3:0> + 1))
Clock source/(2 x 2 x (LP<3:0> + 1))
Clock source/(1 x 3 x (LP<3:0> + 1))
Clock source/(1 x 4 x (LP<3:0> + 1))
Static
FRAME FREQUENCY
FORMULAS
APPROXIMATE FRAME
FREQUENCY (IN Hz) USING
F
32.768 kHz OR INTOSC
85
64
51
43
37
32
OSC
Frame Frequency =
@ 8 MHz, TIMER1 @
OSC
1/2
85
64
51
43
37
32
/8192, T1OSC/32 or
DS41250E-page 107
114
1/3
85
68
57
49
43
1/4
85
64
51
43
37
32